Random pattern self test design

An array logic device of the type having first and second orthogonal sets of lines, means for applying input signals to the lines of the first set, circuit elements located at selected crossover points of the array to establish a pattern of interconnections from the first set to the second set, means for translating signals on the second set of lines to device output signals, means for generating a first plurality of random test signals and means for applying said test signals to said first lines, and means for detecting a function of the signal on said second lines during a test, wherein an improvement for self-testing the logic device comprises,

• means for supplying a second plurality of random signals, and means responsive to the second plurality of random signals for selectively enabling the lines of the first set in a plurality of segments during a test, and
• a second array having third and fourth orthogonal sets of lines, said fourth set of lines being formed as extensions of the lines of the second set, circuit elements at intersections of the third and extension lines in a pattern to disable a plurality of said second lines according to signals on said third lines, means for supplying a third plurality of random signals, and means responsive to said third plurality of random signals for forming signals on said third lines to disable a plurality of said second lines during a test,
• said second and third random signal means being arranged to cooperate with said first random signal means for stepping the device through a predetermined sequence of random test states, whereby after a predetermined number of steps the state of the device can be compared with the state of good device.