Method and means for testing integrated circuits

In an integrated circuit having data processing logic thereon, said data processing logic having a plurality of logic outputs, said integrated circuit further having a plurality of integrated circuit inputs including a reset input, and a plurality of integrated circuit outputs, the improvement comprising:

• first means connected to a number of said plurality of integrated circuit outputs, to a number of said data processing logic outputs, and to said reset input for disabling said number of integrated circuit outputs, in response to assertion of said reset input, so that data on said number of logic outputs cannot reach said number of integrated circuit outputs;
• second means connected to said data processing logic, and to at least one of said number of said plurality of integrated circuit outputs for providing a test flag to said integrated circuit in response to assertion of at least one of said number of integrated circuit outputs;
• and,
• third means connected to said first and second means, said third means including latch means for latching said test signals, in response to a first signal applied to said reset input, to thereby store a test signal state;
• said first means including decoding means connected to said data processing logic outputs, to said plurality of integrated circuit outputs and to said third means, for decoding said test signal state, said decoding means including controlling means for controlling said integrated circuit outputs, depending upon said test signal state, regardless of the condition of said logic outputs;
• said third means including fourth means connected to said latch means and to said reset input, responsive to a second signal on said reset input for unlatching said latch means, to thereby clear said test signal state.

The method of testing a checking integrated circuit having data processing logic thereon, a plurality of inputs including a reset input, and a plurality of outputs, said method comprising the steps of:

• asserting said reset input;
• disabling the outputs of said integrated circuit, in response to said assertion of of said reset input, so that data from said data processing logic cannot reach said outputs;
• asserting a number of said plurality of outputs with test signals thereon to provide test signal inputs to said integrated circuit to thereby provide test signals for said data processing logic;
• disasserting said reset input;
• storing the state of said test signals, in response to said disassertion of said reset input;
• disasserting said number of said plurality of outputs, thereby removing said test signal inputs;
• enabling said outputs of said integrated circuit in selected electrical states, in response to said disassertion of said reset input and in accordance with said stored test signal state;
• reasserting said reset input;
• and,
• clearing the state of said test signals, in response to said reassertion of said reset input.