Semiconductor memory device

A semiconductor memory device formed on a semiconductor substrate, operatively connected to receive first and second control signals, comprising:

• a plurality of bit line pairs;
• sense amplifiers arrayed on the semiconductor substrate, the array of said sense amplifiers having first and second sides, said sense amplifiers, respectively, operatively connected to said bit line pairs;
• first and second data buses respectively disposed on said first and second sides of the array of said sense amplifiers;
• first and second gate elements respectively disposed on said first and second sides of the array of said sense amplifiers and connected between a corresponding bit line of one of said bit line pairs and one of said first and second data buses;
• column decoders, each of said column decoders having first and second sides and being provided for a plurality of said sense amplifiers, for outputting decoded signals;
• first and second control signal lines, respectively disposed on said first and second sides of the array of said senser amplifiers, and operatively connected to receive the first and second control signals, respectively;
• first and second means, respectively disposed on said first and second sides of said column decoders, and operatively connected to receive the first and second control signals, respectively, and operatively connected to receive said decoded signals, for providing gate control signals to said first and second gate elements to control the transfer of signals to and from said first and second data buses and one of said bit line pairs, in dependence upon both said decoded signals and the first and second control signals;
• and
• first and second conducting lines, disposed between the array of said sense amplifiers, for transferring said gate control signals between said first and second sides of the array of said sense amplifiers, each of said first conducting lines being connected between corresponding ones of said first gate elements and corresponding ones of said second means, each of said second conducting lines being connected between corresponding ones of said second gate elements and corresponding ones of said first means.