US 4,546,447 AGranted

Division apparatus

AssigneeHitachi, Ltd.

InventorHideo Sawada

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Abstract

A division apparatus. A quotient of one digit and a remainder are determined by repeating execution of a single type processing of adding an integral multiple of a divisor and an intermediate remainder. The apparatus includes first, second and third registers for storing a dividend or the intermediate remainder, the integral multiple of a divisor and a carry resulted from a preceding operation, respectively, a selection circuit for selecting the complement of the integral multiple of the divisor when the carry is zero while selecting the integral multiple of the divisor when the carry is 0, an arithmetic circuit for performing adding operation on the output of the selection circuit and the content of the first register with the carry being served as the initial carry, and a counter for counting a number which corresponds to the integral multiple of the divisor. The result of the arithmetic operation which is executed in dependence on the value assumed by the carry is placed in the first register. The quotient is determined on the basis of the content of the counter.

Claims3

Dependent claims

An apparatus for division, comprising:

a first register for storing a dividend or an intermediate remainder;
a second register for storing an integral multiple of a divisor;
a third register for storing a carry obtained as part of the result of an arithmetic operation;
complement means connected to said second register for producing the complement of the integral multiple of the divisor;
a selection circuit connected to said second register and to said complement means for selecting the complement of the integral multiple of the divisor when the carry produced during the preceding arithmetic operation is 1 (one) and for selecting the integral multiple of the divisor when said carry produced during the preceding operation is 0 (zero) according to the contents of said third register;
an arithmetic unit for performing addition on the basis of the output of said selection circuit applied to one input and the content of said first register applied to another input with the carry resulted from the preceding operation being utilized as an initial carry;
counter means for counting a number which corresponds to said integral multiple of said divisor;
means for controlling operation of said counter means and said arithmetic unit in dependence on the value by the carry produced during the preceding arithmetic operation is stored in said third register;
and means for placing the result of the arithmetic operation in said first register whereby the quotient is determined on the basis of the content of said counter means.

6 more elements

Dependencies are inferred from the claim text.