Digital processing circuit having a multiplication function
AssigneeNippon Electric Co., Ltd.
InventorToshiaki Machida
Life of this patent
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Abstract
In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.
Claims18
A digital processing circuit for multiplying a multiplicand and a multiplier to produce a multiplication result, comprising:
- first means for storing said multiplicand therein;
- second means for storing said multiplier therein;
- third means coupled to said second means for decoding the multiplier read out of said second means according to Booth's algorithm to thereby produce coefficients;
- fourth means coupled to said third means and said first means for producing partial products by multiplying the multiplicand by said coefficients;
- fifth means for receiving first and second inputs and for executing addition of said first and second inputs, said first input comprising said partial products;
- sixth means for receiving an addition result from said fifth means and feeding back this result as said second input of said fifth means;
- and
- seventh means for outputting said addition result as a multiplication result.
A digital processing circuit for multiplying a multiplicand by a plural bit multiplier to produce a multiplication result, comprising:
- a first memory for storing said multiplicand;
- a second memory for storing said multiplier;
- a decoder for decoding the multiplier in said second memory according to Booth's algorithm to produce coefficients with each coefficient corresponding to a predetermined number of multiplier bits less then the entire number of bits in said multiplier;
- a partial product producing circuit for producing partial products by multiplying the multiplicand in said first memory by the coefficients produced by said decoder;
- an adder circuit for adding together the partial products produced by said partial product producing circuit to produce a multiplication result;
- and
- means for transferring n consecutive multiplier bits in parallel from said second memory to said decoder, where n is equal to said predetermined number.
Dependencies are inferred from the claim text.