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US 4,546,445 AGranted
Systolic computational array
AssigneeHoneywell Inc.
InventorPaul R. Haugen
Life of this patent
Estimating the term…
Abstract
The present invention provides a systolic computational array including two shift registers. Selected ones of the shift register stages are adapted to provide the values contained therein to two multiply-accumulate devices.
Claims4
A systolic computational array comprising:
- a plurality of multiply-accumulate devices, each of said multiply-accumulate devices having a first input means adapted to accept members of a first series of numerical data and a second input means adapted to accept members of a second series of numerical data, each of said multiply-accumulate devices being adapted to accumulate a sum of products of members of said first series of numerical data and members of said second series of numerical data;
- a first shift register having a plurality of stages, each of said stages being adapted to retain a value representative of a member of said first series of numerical data and to provide said value to said first input means of at least one of said multiply-accumulate devices, selected ones of said first shift register stages being adapted to provide said values to said first input means of at least two of said multiply-accumulate devices;
- a second shift register having a plurality of stages, each of said stages being adapted to retain a value representative of a member of said second series of numerical data and to provide said value to said second input means of at least one of said multiply-accumulate devices and selected ones of said stages of said second shift register are adapted to provide said values to at least two of said second input means of said multiply-accumulate devices.
Dependencies are inferred from the claim text.