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US 4,546,444 AGranted
Data compression interface having parallel memory architecture
AssigneeE. I. Du Pont de Nemours and Company
InventorDavid C. Bullis
Life of this patent
Estimating the term…
Abstract
A data compression interface is characterized by a memory system having an architecture configured from a first and a second serial memory connected in parallel. One memory serves during alternate frames as a data collection memory while the other serves during that same frame as an output memory.
Claims27
An inspection system for inspecting a web subdivisible into a series of frames comprising:
- a flying spot generator for generating a flying spot of radiation movable over the web along a plurality of transverse scan paths, each frame comprising a predetermined plurality of scan paths each of which is subdivisible into a number of transversely contiguous lanes;
- a detector for generating a pedestal signal representing the radiation transmitted through or reflected by the web;
- a discriminator responsive to the pedestal for generating a characteristic signal representative of the presence of a predetermined physical property on the web at a corresponding lane of a scan path;
- and
- first and second serial memories connected in parallel, each memory having a number of stages corresponding to the number of lanes, one memory being selectable during alternate frames as an input memory for storing each characteristic signal in the stage corresponding to the lane in which it was generated to produce an accumulated lane-by-lane summary of the occurrence of the property during a frame, while the other memory is selectable as an output memory from which the summary produced during the preceding frame is read.
2 more elements
A web inspection system for inspecting a web material that is subdivisible into a predetermined number of longitudinally extending frames comprising:
- a source of radiation;
- means for moving a spot of radiation transversely of the web along a plurality of generally parallel scan paths, each frame comprising a predetermined plurality of scan paths, each scan path being subdivisible into a predetermined plurality of transversely contiguous lanes;
- a detector responsive to the radiation transmitted through or reflected by the web for generating an electrical pedestal signal representative thereof;
- a discriminator network responsive to the pedestal signal for generating an electrical characteristic signal representative of the presence of a predetermined physical property on the web at a corresponding lane of the scan path;
- first and second serial memories connected in parallel, each memory having a number of stages corresponding to the number of lanes;
- and
- a memory selector network for selecting during each frame one of the memories as an input memory and the other memory as an output memory so that during each frame each characteristic signal from the discriminator representing the presence of the predetermined physical property in a lane along each scan path is storable in the stage of the input memory corresponding to that lane to produce at the end of the frame an accumulated lane-by-lane summary of the occurrence of the predetermined physical property while, the other memory is selectable as an output memory from which the lane-by-lane summary produced during the preceding frame is read.
4 more elements
Dependencies are inferred from the claim text.