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US 4,546,370 AGranted
Monolithic integration of logic, control and high voltage interface circuitry
AssigneeTexas Instruments Incorporated
InventorPatrick A. Curran
Life of this patent
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Abstract
Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.
Claims5
An integrated semiconductor circuit, comprising:
- a self-aligned D-MOS transistor, having a channel region, a source and a drain on opposite sides of said channel region, and a backgate region at least partially within said channel region;
- and a vertical NPN transistor, having an emitter, a base and a collector, said NPN transistor being isolated from said D-MOS transistor to enable high performance operation thereof;
- the D-MOS transistor having a diffused dopant concentration profile in said channel region;
- the emitter of said NPN transistor being formed in a well having a diffused dopant concentration profile corresponding to said dopant concentration profile of said D-MOS transistor channel region;
- whereby said dopant concentration profiles determine the D-MOS transistor threshold voltage.
2 more elements
An integrated semiconductor circuit, comprising:
- a monocrystalline p-type semiconductor substrate;
- a plurality of regions of n-type semiconductor formed upon said substrate, said regions being isolated from each other to enable high performance operation of transistor devices formed therein;
- a plurality of wells of lightly doped p-type material selectively formed within said n-type semiconductor regions;
- a self-aligned D-MOS transistor, in one of said regions, and having a channel formed in one of said wells, a source and a drain on opposite sides of said channel, and a backgate adjacent said channel away from said source and drain;
- and a vertical NPN transistor, in another of said n-type semiconductor regions, and having an emitter, a base and a collector, said base being formed in another one of said wells;
- the well in which said channel of said D-MOS transistor is formed having a diffused dopant concentration profile;
- the well in which the emitter of said NPN transistor is formed having a diffused dopant concentration profile corresponding to said dopant concentration profile of said well in which said channel of said D-MOS transistor is formed;
- whereby said dopant concentration profiles determine the D-MOS transistor threshold voltage.
5 more elements
Dependencies are inferred from the claim text.