Adaptable demodulator for arbitrary amplitude and phase keyed modulation signals
AssigneeReliance Electric Company
InventorW. Larkin Crutcher
Life of this patent
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Abstract
A demodulator for demodulating a received signal which has been modulated in accordance with a modulation scheme which falls within the class of APK modulation. The demodulator uses a phase locked loop (PLL) to recover the carrier. A ROM in the demodulator provides information in both the sweep and locked modes of operation of the PLL to control the PLL. The ROM also provides at its output the digital data which has been encoded at the modulator in accordance with the selected APK scheme. The information stored in the ROM is uniquely determined by the signal points associated with the selected scheme. A modulator for generating the modulated signal received by the demodulator is also disclosed.
Claims27
A demodulator for demodulating data from a received signal which comprises a carrier signal modulated, in accordance with a selected one of a multiplicity of amplitude and phase keyed modulation schemes, by input binary data having a clock associated therewith, said selected scheme giving rise to a multiplicity of signals representative to said input binary data, said demodulator demodulating said input binary data from said received signal by first capturing said received signal and then by maintaining capture when said received signal is captured, said demodulator comprising:
- (a) storage means having stored therein a multiplicity of addressable words each containing information, said information providing at the output of said storage means when one of said words is addressed signals for controlling demodulation of said received signal and said data, said information being uniquely determined by said multiplicity of signals representative of said input binary data;
- (b) means responsive to said received signal for recovering said clock;
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- (c) loop means arranged to operate in a first mode for capturing said received signal and in a second mode for maintaining capture when said received signal is captured, said loop means responsive in both modes of operation to said received signal, said recovered clock and said demodulation control signals for generating a signal for addressing said words dependent upon said received signal, said demodulation control signals controlling which mode said loop means operates in.
A demodulator for demodulating data from a received signal which comprises a carrier signal modulated, in accordance with a selected one of a multiplicity of amplitude and phase keyed modulation schemes, by input binary data having a clock associated therewith, said selected scheme giving rise to a multiplicity of signals representative of said input binary data, said demodulator demodulating said input binary data from said received signal by first capturing said received signal and then by maintaining capture when said received signal is captured, said demodulator comprising:
- (a) storage means having stored therein a multiplicity of addressable words each containing information, said information providing at the output of said storage means when one of said words is addressed first demodulation control signals, a signal for compensating for fast variations in amplitude and said data, said information being uniquely determined by said multiplicity of signals representative to said input binary data;
- (b) means responsive to said received signal for recovering said clock;
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- (c) loop means arranged to operate in a first mode for capturing said received signal and in a second mode for maintaining capture when said received signal is captured, said loop means including:
- (i) means for generating a signal having a controllable frequency and phase, said means responsive in both modes of said loop means operation to said first demodulation control signals for controlling said phase and frequency and which of said modes said loop means operates in;
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- (ii) means responsive in both modes of said loop means operation to said received signal, said controllable frequency and phase means generated signal, said fast amplitude variations compensating signal and said recovered clock for generating said addressing signal.
A demodulator for demodulating data from a received signal which comprises a carrier signal modulated, in accordance with a selected one of a multiplicity of amplitude and phase keyed modulation schemes, by input binary data having a clock associated therewith, said selected scheme giving rise to a multiplicity of signals representative of said input binary data, said demodulator demodulating said input binary data from said received signal by first capturing said received signal and then by maintaining capture when said received signal is captured, said demodulator comprising:
- (a) compensation means responsive to said received signal and a first control signal for compensating for slow amplitude variations in said received signal and for generating first and second compensated signals;
- (b) storage means having stored therein a multiplicity of addressable words each containing information, said information providing at the output of said storage means when one of said words is addressed signals for controlling demodulation of said received signal and said data, said information being uniquely determined by said multiplicity of signals representative of said input binary data;
- (c) means responsive to said first compensated signal for generating said first control signal and for recovering from said compensated signal said clock;
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- (d) loop means arranged to operate in a first mode for capturing said received signal and in a second mode for maintaining capture when said received signal is captured, said loop means responsive in both modes of operation to said first and second compensated signals, said recovered clock and said demodulation control signals for generating a signal for addressing said words dependent upon said received signal, said demodulation control signals controlling which mode said loop means operates in.
A modulator - demodulator, said modulator giving rise to a signal for transmission which comprises a carrier signal modulated, in accordance with a selected one of a multiplicity of amplitude and phase keyed modulation schemes, by input binary data having a clock associated therewith, said selected scheme giving rise to a multiplicity of signals representative of said input binary data, said demodulator for demodulating said input binary data from a received signal which has been modulated in accordance with said selected scheme, said selected scheme giving rise to said multiplicity of signals representative of said input binary data, said received signal having a carrier signal and a clock associated therewith,
- (a) said modulator comprising:
- (i) storage means having stored therein a multiplicity of addressable words arranged in two equal groups, each of said words containing information, said information being uniquely determined by said selected scheme and providing at the outputs of said storage means when a word from each of said groups is addressed a digital signal, said input binary data addressing said words;
- (ii) oscillator means for generating a signal;
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- (iii) processing means responsive to at least said digital signal and said oscillator signal for generating said signals representative of said input binary data dependent upon said input binary data;
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- (b) said demodulator demodulating said input binary data from said received signal by first capturing said received signal and then by maintaining capture when said received signal is captured, said demodulator comprising:
- (i) storage means having stored therein a multiplicity of addressable words each containing information, said information providing at the output of said storage means when one of said words is addressed signals for controlling demodulation of said received signal and said received data, said information being uniquely determined by said multiplicity of signals representative of said input binary data;
- (ii) means responsive to said received signal for recovering said clock;
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- (iii) loop means arranged to operate in a first mode for capturing said received signal and in a second mode for maintaining capture when said received signal is captured, said loop means responsive in both modes of operation to said received signal, said recovered clock and said demodulation control signals for generating a signal for addressing said words dependent upon said received signal, said demodulation control signals controlling which of said modes said loop means operates in.
Dependencies are inferred from the claim text.