Memory identification apparatus and method

A memory system for accessing data words in response to memory requests, each request having an address coded for specifying a data word to be accessed, said memory system comprising:

• a number of identical memory module boards, each including:
• a memory section having a number of rows of addressable memory parts, said number of rows and memory parts selected in constructing said memory section defining different characteristics of said memory module board;
• and
• identification section for generating a plurality of identification signals coded for indicating said different characteristics, said identification section of each of said number of boards being connected in common;
• and
• a main board coupled to each of said number of identical memory module boards, said main board including decoder circuit means being coupled to said identification and memory sections of each memory module board and for receiving a predetermined multibit address portion of said address of each request, said decoder circuit means being conditioned by said identification signals for decoding different address bit combinations of said predetermined multibit address portion selected as a function of said coded identification signals to generate said number of said row decode selection signals in a manner for successively addressing of said pluralities of storage locations within each of said rows of said number of identical memory module boards.

A method of constructing a memory system having a main board and a number of identical memory module boards with different types of memory parts and having different board densities, said method comprising the steps of:

• constructing each of said memory module boards to include a memory section and an identification section;
• constructing said memory section of each of said memory module boards to accommodate the type of said memory part having the largest number of bit locations;
• mounting permanently in said memory section, a number of addressable memory parts of one of said types positioned in blocks so as to provide a given one of said densities;
• constructing said identification section for generating identification signals coded for indicating said type of memory part and said board density;
• connecting said identification section of each board in common, so as to provide a single set of said coded identification signals;
• constructing said main board to include decoder circuit means, having a number of output terminals;
• connecting said decoder circuit means to receive a predetermined multibit address portion of the address of each memory request applied to said system and connecting said decoder means to decode different address bit combinations of said predetermined multibit address portion as a function of said coded identification signals and generate a number of row decode selection signals on said output terminals;
• and
• selectively connecting groups of said output terminals to different ones of said memory module boards for enabling the successive addressing of said blocks of said memory parts of said number of boards.

A computer memory comprising a plurality of memory module boards connected to a memory control board, wherein said memory control board receives addresses representing a particular storage location of one of said module boards and responds by causing information to be written into or read out therefrom, said memory comprising:

• each of said memory module boards including:
• a plurality of addressable chip storage units, each of said chip storage units being coupled to receive address signals representing a particular storage location to be accessed;
• circuit means for receiving chip storage unit selection denoting signals and for coupling each of said selection denoting signals to a respective one of said chip storage units, each of said selection denoting signals when in a predetermined state enabling the corresponding chip storage unit to perform a cycle of operation upon the addressed storage location;
• and,
• identification circuit means for delivering identification signals indicating the type of chip storage units and the populated density of said memory module board, and
• said common memory control board comprising:
• decoding circuit means coupled to receive said identification signals and conditioned to perform a particular decoding function in response to the collective states of said signals;
• and,
• circuit means adapted to receiving said address signals and to apply a subset of said signals to said decoding circuit, said decoding circuit, as conditioned by said identification signals, decoding said signal subset to deliver to said chip storage unit, said selection denoting signals in which one of said signals is in said predetermined state.