Formation of normal resistors by degenerate doping of substrates
AssigneeSperry Corporation
InventorHarry Kroger
Life of this patent
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Abstract
In superconductive integrated circuit a semiconductor substrate is used in combination with normal resistors formed by degenerate doping of the substrate in selected regions. Doping is preferably performed by planar diffusion or ion implantation. Application of the invention to fabrication of a Josephson Atto-Weber gate by forming a normal resistor intermediate the junctions is also disclosed.
Claims17
A tunnel junction device for use as a gate in superconductive circuits, comprising;
- a semiconductive substrate,
- a degeneratively doped region within said substrate, said degenerately doped region defining a normal resistance at superconducting temperatures,
- first and second regions comprising a first layer of superconductive material spaced apart and superposed over at least portions of said normal resistance and in contact therewith,
- a barrier layer deposited on said first layer of superconductive material,
- a second layer of superconductive material superposed with respect to said barrier layer, and having at least one opening therethrough defining a tunneling junction area,
- an insulating layer deposited on said second layer of superconductive material, having an opening defining said tunneling junction area, and
- a third layer of superconductive material, superposed with respect to said insulating layer and said junction area of said barrier for electrical contact to said barrier layer.
A current switched Josephson gate comprised of a semiconductive substrate, at least two Josephson tunnel junctions on said substrate, a normal resistance intermediate said junctions formed by degenerate doping of a predetermined region of said semiconductive substrate, said junctions having respective contact electrodes deposited on said region, and means for coupling a control current, offset current, bias current and a load to said junctions, so that said control current causes switching of said gate from the zero voltage state to a non-zero voltage state.
A superconductive logic circuit, comprising:
- a degenerately doped semiconductor substrate,
- an epitaxial semiconductor layer superposed thereon,
- a plurality of degenerately doped regions and nondegenerately regions disposed in said epitaxial layer,
- a plurality of superconductive logic gates deposited on said epitaxial layer, each of said gates having a junction area superposed on a non-degenerately doped region of said layer,
- at least two of said gates having a contact area superposed on and adjoining one of said degenerately doped regions;
- at least one layer of superconductive material superposed on said at least two of said gates and said one degenerately doped region.
Dependencies are inferred from the claim text.