Driving circuit for an electrostatic recording head

A circuit comprising a plurality of driving circuits for driving an electrostatic recording head with high voltage driving output pulses having a reduced trun-off, storage and turn-off time, each driving circuit comprising:

• mutually complementary first and second transistors each having a base and emitter and commonly interconnected collectors;
• a first input terminal, for receiving a first driving signal, coupled to the base of said first transistor and to the base of said second transistor;
• means for producing said first driving signal;
• a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor;
• means for producing said second driving signal;
• a third input terminal, for receiving a third driving signal, coupled in parallel with said first input terminal;
• a high voltage potential coupled to the emitter of said first transistor;
• an output terminal coupled to the interconnection of the collectors of the first and second transistors;
• the first driving signal corresponding to picture signals to be recorded by the recording head and having at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period;
• said second driving signal having at least first and second non-zero signal levels, the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of the second non-zero signal level of said first driving signal and
• said third driving signal representing either an open circuit condition or a grounded condition.

In a driving circuit for producing high voltage driving output pulses for driving an electrostatic recording head, said circuit comprising:

• mutually complementary first and second transistors, each having a base and emitter and commonly interconnected collectors;
• a first input terminal, for receiving a first driving signal corresponding to picture signals to be recorded by the recording head, coupled to the base of said first transistor and to the base of said second transistor;
• a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor;
• a high voltage potential source coupled to the emitter of said first transistor;
• and an output terminal coupled to the interconnection of the collectors of said first and second transistors;
• a method of reducing turn-on time, storage time and turn-off time of said high voltage output pulses comprising the steps of:
• applying said first driving signal to said first input terminal wherein said first driving signal has at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period;
• and,
• applying said second driving signal to said second input terminal wherein said second driving signal has at least first and second non-zero signal levels, the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of first driving signal.