Digital code translator
AssigneeAT&T Bell Laboratories
InventorCraig A. Sharper
Life of this patent
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Abstract
The most significant bits of each input word of a linear PCM signal address a read-only memory (ROM). Stored at each ROM address is a table of instruction words, one instruction word for each bit in the output word. The instruction words direct a switch to select each bit for the output word from a choice of 1, 0, or an input bit PCM compression according to a predetermined characteristic is implemented by instruction words which direct selection of the proper chord bits from 1 or 0 and the proper step bits from the input bits. A different compression characteristic may be implemented by a different set of stored instruction words. The instruction words also command selective bit inversion and selective inclusion of the bit in a parity check. Implementation of the translator with commercially available hardware is described.
Claims7
A digital code translator for translating an input PCM word according to a predetermined compression characteristic into an output PCM word having chord bits and step bits, said translation comprising:
- memory means (41, 141) having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs (A4-A9) and instruction word outputs (Q0-Q5);
- means connecting a first predetermined selection of bits of said input word to said address inputs;
- selector switch means (45, 148, 150, 152) having instruction inputs connected to said instruction word outputs to receive said instruction words, a plurality of bits inputs (0-15), and a switch output (51, 161) for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word;
- means connecting a source of potential representative of a "1" inputs;
- means connecting a source o potential representative of a zero to a second one of said bit inputs;
- and
- means connecting a second predetermined selection of bits of said input word to others of said bit inputs, respectively;
- respective instruction words of said tables directing said switch to select said chord bits from among said first and second ones of said bit inputs and to select said step bits from among said others of said bit inputs according to said predetermined compression characteristic to generate said output word.
Dependencies are inferred from the claim text.