Circuit arrangement for monitoring speed of a drive motor

Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means responsive to said output signal for providing an alarm signal when the amplitude of said output signal reaches a value corresponding to an increases of the motor speed above a predetermined maximum speed, said evaluation circuit having a predetermined delay exceeding the acceleration time of said motor to prevent the provision of said alarm signal during starting of said motor.

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay.

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to a drop below a predetermined minimum speed, said evaluation circuit having a latch function for said recognition signal.

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, said evaluation circuit being provided with its own power supply.

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay.

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to an increase over a predetermined maximum speed, said evaluation circuit having a latch function for said recognition signal.

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, said evaluation circuit being provided with its own power supply.