US 4,543,652 AGranted

Time-division switching unit

AssigneeHitachi, Ltd.

InventorsEiichi Amada, Hiroshi Kuwahara, Hirotoshi Shirasu, Taihei Suzuki, Takashi Morita

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Abstract

A time-division switching unit for connecting a desired channel of a desired one of a plurality of input highways to a desired channel of a desired one of a plurality of output highways is disclosed. A frame synchronization circuit of the time-division switching unit variably delays signals of the input highways within one channel period, writes the signals to a speech memory for each channel, modifies write addresses to the speech memory to attain frame synchronization, extracts frame synchronization signals of the respective highways from the input and output of the speech memory, and controls the amount of delay within one channel period and the amount of address modification by the extracted synchronization signals.

Claims15

Dependent claims

A time-division switching unit for writing into first memory means signals of a plurality of input highways including time-division multiplexed signals of a plurality of channels in one frame and connecting a desired channel of a desired one of said plurality of input highways to a desired channel of a desired one of a plurality of output highways by controlling write and read addresses to said first memory means, comprising:

(a) a plurality of bit synchronization circuits provided one for each of said plurality of input highways;
(b) multiplexer means for multiplexing outputs of said bit synchronization circuits;
(c) address control means for controlling addresses to write and read the output of said multiplexer means to and from said first memory means;
(d) distribution means for distributing signals read from said first memory means to said plurality of output highways;
(e) frame synchronization signal detecting means for detecting a frame synchronization signal of the input highway from the input of said first memory means;
and
(f) a frame synchronization circuit for modifying the write address determined by said address control means in accordance with the output of said frame synchronization signal detecting means and variably delaying the signals of said input highways within a range of one channel period.

4 more elements

A time-division switching unit for writing into first memory means signals of a plurality of input highways including time-division multiplexed signals including a control information channel in one frame and controlling write and read addresses to said first memory means to connect a desired channel of a desired one of said plurality of input highways to a desired channel of a desired one of a plurality of output highways, comprising:

(a) multiplexer means for time-division multiplexing the time-division multiplexed from said plurality of input highways;
(b) address control means for controlling addresses to write and read the output of said multiplexer means to and from said first memory means;
(c) distribution means for distributing the signals read from said first memory means to said plurality of output highways;
(d) a frame synchronization circuit including frame synchronization signal detecting means for detecting frame synchronization signals of the input highways from the inputs of said first memory means, and means for modifying the write address determined by said address control means by the output of said frame synchronization signal detecting means and variably delaying the signals of said input highways within one channel period;
(e) a control information transceiver including:
an input buffer;
a first input/output buffer control circuit for detecting a specified channel position of the control information of the input highway from the output of said first memory means by at least a portion of an output of a reference counter for said address control means and writing the control information of said input highway into a specified position of said input buffer;
an output buffer;
and
a second input/output buffer control circuit for sending out the control information stored in said output buffer to a specified channel position of the output of said first memory means by at least a portion of the output of said reference counter;
and
(f) a processor for reading out the control information of the input highway written in said input buffer and writing into said output buffer the control information to be sent out to said output highway.

9 more elements

Dependencies are inferred from the claim text.