Electrically programmable non-volatile semiconductor memory device

An electrically programmable non-volatile semiconductor memory device, comprising:

• a first group of address buffers;
• a row decoder operatively connected to said first group of address buffers and having outputs;
• word lines operatively connected to the outputs of said row decoder;
• a second group of address buffers;
• a column decoder operatively connected to said second group of address buffers and having outputs;
• column decoder output lines connected to the outputs of said column decoder;
• power down means, operatively connected to said first and second groups of address buffers, for placing said first and second group of said address buffers in a power down mode by applying a power down mode signal thereto;
• bit lines which are selected in dependence upon the output of said column decoder output lines;
• bit line selection means, operatively connected between said column decoder output lines and said bit lines, for selecting said bit lines in dependence upon the output of said column decoder output lines;
• a memory array of cell transistors which are operatively connected at the cross points of said word lines and said bit lines and each memory array cell transistor has a source connected to ground, a control gate connected to one of said word lines, a drain connected to one of said bit lines and a floating region for storing electric charge, information "0" is written in the respective cell transistor by placing the respective selected word line and the respective selected bit line at a first potential at the same time, information "1" is written in the respective cell transistor by placing the respective selected word line at the first potential and the respective selected bit line at a second potential;
• and
• at least one control circuit, operatively connected to said first group of address buffers, said second group of address buffers and said power down means, for placing, at a test time, a plurality of said word lines and/or a plurality of said bit lines in a selected state at the same time.

An electrically programmable non-volatile semiconductor memory device, comprising:

• a memory cell array having memory cells with word and bit lines;
• an input circuit, operatively connected to the bit lines in said memory cell array, for applying a write signal to all memory cells and having active and inactive states;
• a decoder operatively connected to the word and bit lines of said memory cell array and including an address buffer;
• control means, operatively connected to said address buffer, for simultaneously placing the word and/or bit lines of said memory cell array in a selected state and placing said input circuit in the active state;
• and
• powder down means, operatively connected to said decoder and said input circuit, for placing said decoder and said input circuit in a power down mode at a power down time, and in said power down mode all of said word lines and/or all of said bit lines being in a selected state at the same time and said input circuit being in the inactive state.

An electrically programmable non-volatile semiconductor memory device operatively connected to receive a power down signal at a power down time and an address signal, said device comprising:

• a memory cell array having memory cells and bit and word lines connected thereto;
• a decoder operatively connected to the bit and word lines of said memory cell array;
• an address buffer operatively connected to said decoder and operatively connected to receive the address signal;
• control means, operatively connected to said address buffer and to receive a test signal, for simultaneously placing the memory cells of said memory cell array in a selected state, said control means supplying a control signal to said address buffer when receiving the address signal at a test time or when receiving the power down signal at the power down time so that the decoder selects all of the word lines and/or all of the bit lines, and said control means comprising:
• a first inverter operatively connected to receive the address signal;
• a second inverter operatively connected to said first inverter and to receive the power down signal;
• and
• a third inverter operatively connected to said second inverter and said address buffer.