Control circuit for matrix-driven recording

A control circuit for matrix drive recording comprising:

• a microprocessor;
• an address bus and a data bus;
• a random access memory connected to said microprocessor through said address and data buses;
• a multiplexer circuit having a first address input connected to said address bus to receive a first address and a second address input connected to receive a second address and having an address output connected to said random access memory for changing over said first and second addresses to said random access memory;
• an exclusive OR circuit having a plurality of two-input exclusive OR gates, each output of which is connected to supply a predetermined input address bit of said second address from said address bus to said multiplexer circuit, one of the two inputs of said plurality of exclusive OR gates being connected to receive one among a plurality of bits of said address bus and the other of said two inputs being connected to receive a respective one of the other bits of said address bus;
• a shift register connected to said data bus for inputting parallel data from said random access memory and for shifting the data sequentially to provide the data in series;
• and
• a direct memory access controller connected to said address bus for controlling data transfer from said random access memory to said shift register and for providing an acknowledge signal to said multiplexer to control the change over of said multiplexer circuit at the time of said data transfer.