Analog-to-digital correlator with programmable coefficients with values of +1, -1 or 0

An analog-to-digital correlator, with programmable correlation coefficients with values of +1, -1, or 0, which comprises:

• a multi-stage analog charge-transfer shift register (1) receiving samples of an input analog signal (E) for correlation, each stage (e) thereof including at least one reading electrode;
• means (2) for multiplying by +1 or 0 the signal at the output from each stage (e) of the charge-transfer register;
• means (3) for multiplying by +1 or -1 the output signal, from each stage of the charge-transfer register, not cancelled by said means for multiplying by +1 or 0,
• said means (3) for multiplying by +1 or -1 comprising two parallel charge-reading tracks, one of said tracks being connected to the positive input of said differential amplifier, and the other of said tracks being connected to the negative input of said amplifier,;
• two shift registers (4, 5) with programmable digital outputs with values of 0 or 1, the respective outputs of the two shift registers being connected to two memories (m, M),
• one (m) of said memories controlling said means (2) for multiplying by +1 or 0, and the other (M) of said memories controlling said means (3) of multiplying by +1 or -1,
• said digital-output registers (4, 5) selectively controlling outputs of said charge-reading tracks to one of two conditions, reading or blocking of reading;
• a differential amplifier (8) having a positive input and a negative input;
• means (6) for algebraic adding of output signals of said respective means for multiplying, and
• means (7) for reading charges, so as to obtain an electric output signal (S) from the correlator, said means for reading charges comprising:
• a first group of metal-oxide-semiconductor (MOS) transistors connected, on each reading track, on the one hand, to the reading electrode of each stage (e) of the analog register (1), and, on the other hand, to one of said inputs of said differential amplifier (8);
• a pair of capacitors, each being connected between ground and a respective input of said differential amplifier (8);
• a control circuit connected to each differential amplifier input, responsible for charging said capacitor and for saturation of said first group of MOS transistors, before arrival of charges to be read beneath the reading electrodes, the capacitor potential being left floating during arrival of charges;
• a second group of MOS transistors connected between the reading electrode of each stage of said analog register and a reference potential, said transistors blocking reading during intervals when quantities of charge for reading are not beneath the reading electrodes;
• said (2) means for multiplying by +1 or 0 comprising:
• a third group of MOS transistors, connected by their collectors and sources between the reading electrode of each stage of the charge-transfer shift register and the reference potential, said transistor being controlled by signals delivered by memories connected to one of the digital-output registers;
• said means (3) for multiplying by +1 or -1 comprising:
• a fourth group of MOS transistors, connected in series by their collectors and emitters with said first group of MOS transistors, their gates being controlled by signals delivered by memories connected to one of said digital-output registers.