US 4,543,627 AGranted

Internal communication arrangement for a multiprocessor system

AssigneeAT&T Bell Laboratories

InventorThomas F. Schwab

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Abstract

A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating processors via direct memory access circuits. A sending processor stores messages in a send buffer in memory of the sending processor and controls a pointer in that memory indicating the loading of message into that buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another. Initialization of the interface processor is a joint effort of the communicating processors.

Claims8

Dependent claims

A multiprocessing system comprising:

a first processor for generating first data messages and having first memory means for storing said first data messages at locations defined by a first load address indicator and a first unload address indicator;
a second processor for receiving said first data messages and having second memory means for storing said first data messages at locations defined by a second load address indicator and a second unload address indicator;
and
means for controlling the transmission of data between said first and said second processor comprising:
first and second memory data transfer controllers connected to said first and said second memory means, respectively, and responsive to read and write control signals for reading from and writing into said connected memory means, and an interface processor, interposed between said first and said second memory data transfer controllers, for detecting a change in said first load address indicator, and for generating said read control signals to cause said first memory data transfer controller to read said first data messages from said first memory means at locations defined by said first load address indicator and for generating said write control signals to cause said first memory data transfer controller to modify said first unload address indicator to alter a limit of the locations in which said first processor can store new data messages and for generating said write control signals to cause said second memory data transfer controller to write said first data messages into said second memory means at locations defined by said second load address indicator and to modify said second load address indicator after said first data messages have been stored in said second memory means.

2 more elements

A multiprocessing system comprising:

a first processor for generating first data messages having first memory means for storing data messages at locations defined by a plurality of first load address indicators and first unload address indicators;
a plurality of second processors, each comprising a load address indicator and unload address indicator, for receiving said first data messages and each having memory means for storing data messages at locations defined by the load and unload address indicators for that second processor;
and means for controlling the transmission of data between said first processor and said plurality of second processors comprising:
a first memory data transfer controller connected to said first memory means and responsive to read and write control signals for reading from and writing into said first memory means and a plurality of second memory data transfer controllers each connected to said memory means of one of said plurality of second processors and responsive to read and write control signals for reading from and writing into said connected memory means;
interface processor means interposed between said first memory data transfer controller and said plurality of second memory data transfer controllers for detecting a change in one of said first load address indicators, for generating read control signals to cause said first memory data transfer controller to read first data messages from said first memory means at locations defined by said one of said first load address indicators, and for generating write control signals to cause said first memory data transfer controller to modify the one of said first unload address indicators corresponding to said first one of said load address indicators to alter a limit of the locations in which said first processor can store new first data messages, and for generating write control signals to cause a selected one of said plurality of second memory data transfer controllers to write said first data messages read from said first memory means into the memory means connected to said selected one of said second memory data transfer controllers and associated with the corresponding selected one of said second processors of locations defined by a load address indicator of said selected one of said plurality of second processors, and to cause said memory data controller to modify said load address indicator of said selected one of said second processors after said first data messages have been stored into said memory means associated with said selected one of said second processors.

2 more elements

In a multiprocessing system comprising a plurality of processors each having memory means for generating and storing data messages at locations defined by a first load address indicator and a first unload address indicator and for receiving and storing received data messages at locations defined by a second load address indicator and a second unload address indicator, means for controlling the transmission of data between any two processors comprising:

a plurality of memory data transfer controllers each connected to one of said memory means and responsive to read and write control signals for reading and writing into the connected memory means, and interface processor means connected to each of said memory data transfer controllers for detecting changes in the first load address indicator of a selected one of said processors and for generating said read control signals to cause the selected one of said memory data transfer controllers connected to the memory means of said selected one of said processors to read data messages from the memory means of said selected one of said processor at locations defined by said first load address indicator of said selected one of said processor and for generating said write control signals to cause said selected one of said memory data transfer controllers to modify the first unload address indicator of said selected one of said processors to alter a limit of the memory locations at which said selected one of said processors can store new data messages and for generating said write control signals to cause an other of said memory data transfer controllers to write messages read from said selected one of said processors into the memory means connected to said other memory data transfer controllers of an other selected processor at locations defined by a second load address indicator of said other selected processor and to modify said second load address indicator of said other selected processor after said data messages have been stored in said memory means connected to said other selected processor.

In a multiprocessing system comprising a first processor having first memory means and a second processor having second memory means, first and second memory data transfer controllers connected to said first and second memory means respectively, and responsive to read and write control signals for reading and writing into said connected memory means, and an interface processor interposed between said first and second memory data transfer controllers for generating said read and write control signals to control said first and said second memory data transfer controllers, a method for transferring a data message from said first memory means to said second memory means comprising the steps of:

storing a first data message at locations in said first memory means defined by a first load address indicator and a first unload address indicator and modifying said first load address indicator by said first processor;
detecting changes in said first load address indicator by said interface processor;
reading said first data message from said first memory means in accordance with addresses defined by said first load address indicator by said interface processor;
writing from said interface processor said first data message into said second memory means in accordance with addresses defined by a second load address indicator and a second unload address indicator;
modifying said second load address indicator by said interface processor after said first message has been stored in said second memory;
verifying integrity of said first message by said second processor;
modifying said second unload address indicator by said second processor after said first message has been verified;
and
reading said second unload address indicator by said interface processor and modifying said first unload address indicator by said interface processor after said second unload address indicator has been so modified.

6 more elements

Dependencies are inferred from the claim text.