Two-stage high resolution digital-to-analog converter

A two-stage cascaded digital-to-analog converter wherein the first stage comprises a series-connected string of resistors energized by a source of voltage so that the resistor taps present progressively differing voltage levels;

• said string of resistors being sub-divided into successive groups each having four resistors presenting five taps, with the fifth tap of one group serving as the first tap of the next adjacent group;
• an improved switch arrangement for selecting pairs of adjacent taps in accordance with higher-order code bits, thereby to develop segment voltages to be directed to the second converter stage for interpolation in accordance with lower-order bits, said switch arrangement comprising:
• a first set of switch pairs comprising first and second switches having input and output terminals, the input terminals of each pair being connected respectively to the second and fourth taps of a corresponding one of said resistor groups;
• the output terminals of each pair of said first set of switch pairs being connected together to form a first set of output nodes;
• a second set of switch pairs comprising first and second switches having input and output terminals, the input terminal of each pair being connected respectively to the third and fifth tap of a corresponding one of said resistor groups;
• the output terminals of each pair of said second set of switch pairs being connected together to form a second set of output nodes;
• a third set of switches having input and output terminals, each of said third set of switches being associated with a corresponding one of said second set of switch pairs;
• each of said output terminals of said third set of switches being connected respectively to the output node of its corresponding pair of switches;
• the input terminal of each one of said third set of switches being connected to the first tap of the group of resistors associated with said corresponding second set of switch pairs;
• and
• switch activating means for controlling said switches to select any pair of adjacent taps in accordance with a set of code bits.

A two-stage cascaded digital-to-analog converter wherein the first stage comprises a series-connected string of resistors energized by a source of voltage so that the resistor taps present progressively differing voltage levels;

• said string of resistors being sub-divided into successive groups of equal numbers of resistors having taps to which connection can be made, the end tap of one group serving as the first tap of the next adjacent group;
• an improved switch arrangement for selecting any pair of adjacent taps in accordance with a higher-order set of code bits, thereby to develop a segment voltage to be delivered to said second stage converter for interpolation in accordance with a lower-order set of code bits, said switch arrangement comprising:
• a first set of switch groups each comprising a plurality of switches for making connection to any one of a first set of alternate taps of a corresponding resistor group and to produce the selected voltage level on a corresponding output node;
• a second set of switch groups each comprising a plurality of switches for making connection to any one of a second set of alternate taps of a corresponding resistor group and to produce the selected voltage level on a corresponding output node;
• said first and second sets of alternate terminals being interleaved;
• a third set of switches each assigned to a corresponding one of said second set of switch groups;
• the output terminals of said third set of switches being connected respectively to the output nodes of the assigned switch groups;
• the input terminal of said third set of switches being connected respectively to an end tap of the resistor group corresponding to the assigned switch group;
• and
• switch activating means for controlling said switches to provide for selecting any pair of adjacent voltage taps in accordance with the higher-order set of code bits.

A two-stage cascaded D/A converter formed on a single monolithic IC chip for converting a 16-bit word into a corresponding analog signal, and wherein the first stage comprises a 256-R resistor string connected to a switch selector system to produce segment voltages representing the voltage between any two adjacent taps of the resistor;

• said resistor string comprising an elongate geometrically flat strip of Silicon Chronium formed on said IC chip as a single geometrically homogeneous element, free from folding or serpentine patterns;
• means to apply a voltage to the ends of said elongate strip;
• a plurality of selector switches formed along-side said elongate flat strip, on both sides thereof;
• and
• means connecting said switches to evenly-spaced points along the side edges of said strip.