Switched capacitor circuit with minimized switched capacitance

In a filter circuit having an input terminal and an output terminal, said filter circuit having amplifying means with an input and an output terminal, a feedback circuit coupled between the amplifying means input and output terminals, said filter circuit output terminal being coupled to said amplifying means output terminal, said filter circuit comprising circuit components integrated on a monolithic or film stratum having a practical minimum unit of capacitance defined as a MUC, that improvement comprising:

• a first switched capacitor circuit having first and second end terminals and having a first terminal capacity therebetween, with said first and second end terminals being coupled to said amplifying means input and output terminals, respectively;
• a capacitor circuit having first and second terminals coupled to said amplifying means input and output terminals, respectively, and having a second terminal capacity, more than said first terminal capacity, whereby a first ratio "R1" of said second terminal capacity to said first terminal capacity is greater than one;
• said first switched capacitor circuit comprising a number "N" of series connected capacitors, said number N being greater than one and less than said ratio R1;
• each of said series connected capacitors having a first connection point at one plate of said each capacitor and a second connection point at the other plate of said each capacitor;
• said series connected capacitors including a first and a last capacitor and the remaining capacitors of said series connected capacitors being connected in series between said first and last capacitors at said connection points;
• said first connection point of said first capacitor being coupled to said first end terminal of said first switched capacitor circuit and said second connection point of said last capacitor being coupled to said second end terminal of said first switched capacitor circuit;
• said first connection points of said remaining capacitors and said last capacitor being connected to respective second connection points of respective next adjacent capacitors at respective junctions;
• parasitic capacitances being associated with said series connected capacitors;
• discharge circuit means for providing capacitor plate discharge to a reference potential;
• clock phase means for providing in alternation first and second clock phases at a predetermined frequency;
• first and second switching means controlled by said clock phase means and connected to said first and second end terminals respectively of said first switched capacitor circuit for coupling said first and second end terminals to the amplifying means input and output terminals respectively during said first clock phase and uncoupling said first and second end terminals from the amplifying means input and output terminals respectively during said second clock phase;
• a plurality of third switching means controlled by said clock phase means, a said third switching means connected to each said first and second end terminals and to said junctions in said first switched capacitor circuit for coupling each plate of each of said plurality of series connected capacitors to said discharge circuit means for discharging each plate of each of said number N of capacitors in said first switched capacitor circuit at said predetermined frequency to said discharge circuit means during said second clock phase to reduce the effects of parasitic capacities associated with said first switched capacitor circuit and for uncoupling each plate of each of said plurality of series connected capacitors from said discharge circuit means during said first clock phase.