Offset compensated switched capacitor circuits
AssigneeThe Regeants of University of Calif.
InventorsGabor C. Temes, Kenneth W. Martin
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Abstract
A switched capacitor type amplifier system including an operational amplifier is provided with compensating capacitive coupling during the non-sampling portion of the cycle from the output of the operational amplifier to its input, to avoid output discontinuities, and to provide compensation for the offset voltage of the operational amplifier. The circuit includes a two phase clock, with the signal input to the input capacitor being alternately sampled and blocked, and the capacitive compensation circuit mentioned above being alternately blocked and connected, respectively, during successive phases of the clock operation. Special circuitry for preventing "clock feed-through" and for implementing a Multiplying Digital to Analog Converter, or MDAC, are disclosed.
Claims17
A low slew rate switched capacitor system including sampling and reset intervals during each cycle of operation of said system, comprising:
- an operational amplifier;
- an input capacitor connected to one input of said operational amplifier;
- means for receiving a source of input signals to be amplified and applying such signals to said input capacitor;
- a feedback capacitor connected in circuit between the said one input and the output of said operational amplifier;
- a compensating capacitor connected in a second circuit between the output of said operational amplifier and said one input to said operational amplifier;
- and
- switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for first, connecting said input capacitor to the signal source and said feedback capacitor in circuit from said one input to the output of said integrating amplifier, while isolating said compensating capacitor;
- and secondly, opening the circuitry from said signal source to said input capacitor, and from said feedback capacitor to said output, while concurrently closing the circuit including said compensating capacitor, and grounding the input to said input capacitor.
A low slew rate switched capacitor digital to analog conversion system including sampling and reset intervals during each cycle of operation of said system, comprising:
- an operational amplifier;
- an input capacitor array connected to one input of said operational amplifier;
- means for receiving an input signal and applying such signal to said input capacitor array;
- a feedback capacitor connected in circuit between the said one input and the output of said operational amplifier;
- a compensating capacitor connected in a second circuit between the output of said operational amplifier and said one input to said operational amplifier;
- switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for first, connecting said input capacitor to the signal source and said feedback capacitor in circuit from said one input to the output of said integrating amplifier, while isolating said compensating capacitor;
- and secondly, opening the circuitry from said signal source to said input capacitor, and from said feedback capacitor to said output, while concurrently closing the circuit including said compensating capacitor, and grounding the input to said input capacitor;
- and
- said input capacitor array including a plurality of parallel input capacitors, with the capacitors having capacitance values related to one another by powers of two, and associated switching circuitry for selectively either isolating individual input capacitors or placing them in parallel circuit relationship with the other input capacitors;
- whereby the output from said operational amplifier is an analog representation of a digital signal indicated by the array of parallel input capacitors.
A low slew rate switched capacitor system including sampling and reset intervals during each cycle of operation of said system, comprising:
- an operational amplifier;
- an input capacitor connected to the inverting input of said operational amplifier;
- means for receiving a source of input signals to be amplified and applying such signals to said input capacitor;
- a feedback capacitor connected in circuit between said inverting input and the output of said operational amplifier;
- a compensating capacitor connected in a second circuit between the output of said operational amplifier and said inverting input to said operational amplifier;
- and
- switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for sampling said input signals, and for alternately switching said feedback capacitor and said compensating capacitor in circuit between inverting input and the output of said operational amplifier.
Dependencies are inferred from the claim text.