High performance dynamic sense amplifier voltage boost for row address lines

A dynamic semiconductor memory device of the type having an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line and sense amplifiers connected to sense nodes for column lines, each memory cell having an access transistor and a storage capacitor for storing a zero-level or a one-level, comprising:

• a pair of cross-coupled driver transistors for each sense amplifier, each of the driver transistors having a current path and a control electrode,
• means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node,
• grounding means for coupling the grounding node to a reference potential,
• means for precharging the sense nodes to a voltage level prior to an active operating cycle,
• means for applying an address voltage to a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, said address voltage having a magnitude substantially higher than said voltage level during at least part of such active operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored,
• means for applying a clock voltage to activate said grounding means at a first time subsequent to the said given time in the beginning of an active operating cycle,
• pull-up means coupled to the column lines to cause a column line for which a one-level was stored to be pulled up to said voltage level after said grounding means is activated.

A dynamic semiconductor memory device comprising:

• an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line,
• a plurality of sense amplifiers connected to sense nodes on the column lines,
• each memory cell having an access transistor and a storage capacitor for storing data as a one-level or a zero-level,
• each sense amplifier having a pair of cross-coupled driver transistors, each of the driver transistors having a current path and a control electrode, with means connecting the current path of each one of the driver transistors separately between one of the sense nodes and grounding means,
• means for precharging the column lines to a voltage level prior to an active operating cycle,
• pull-up means coupled to the column lines to pull a column line for which a one-level is stored up to said voltage level after the beginning of an active operating cycle,
• and means for applying an address voltage to a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, said address voltage having a magnitude substantially higher than said voltage level during at least part of such active operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored.