Method for forming aluminum oxide dielectric isolation in integrated circuits

#With the ever increasing microminiaturization of semiconductor integrated circuits, and thus increasing lateral semiconductor device densities in integrated circuits, in recent years a major portion of the integrated circuit art has been moving in the direction of utilizing various forms of lateral dielectric isolation in order to laterally electrically isolate the densely packed devices from each other.

#One approach for forming lateral dielectric isolation which has been increasingly utilized in the art involves the formation of recessed silicon dioxide lateral isolation regions, usually in the epitaxial layer where the semiconductor devices are to be formed, through the expedient of first selectively etching a pattern of recesses in the layer of silicon, and then thermally oxidizing the silicon in the recesses with appropriate oxidation blocking masks, e.g., silicon nitride masks, to form recessed or inset regions of silicon dioxide which provide the lateral electrical isolation. Representative of the prior art teaching in this area are U.S. Pat. No. 3,648,125 and an article entitled, "Locos Devices", E. Kooi et al, Philips Research Report 26, pp. 166-180 (1971).

#While this approach has provided good lateral dielectric isolation, it has encountered some problems. Originally, the art applied the silicon nitride masks directly onto the silicon substrates. This gave rise to problems associated with high stresses created on the underlying silicon substrate by the silicon nitride-silicon interface. Such stresses were found in many cases to produce dislocations in the silicon substrate which appear to result in undesirable leakage current pipes and otherwise adversely affect the electrical characterisitics of the interface. In order to minimize such interface stresses with silicon nitride layers, it has become the practice in the art to form a thin layer of silicon dioxide between the silicon substrate and the silicon nitride layer. During such thermal oxidation, there is a substantial additoinal lateral penetration of silicon oxide from the thermal oxidation beneath the silicon nitride. This lateral penetration is greatest at the mask-substrate interface to provide a laterally sloping structure known and recognized in the prior art as the undesirable "bird's beak".

#FIGS. 1A-1G are diagrammatic sectional views of a portion of an integrated circuit in order to illustrate the method of the preferred embodiment of the present invention.

#FIGS. 2A-2G are diagrammatic sectional views of an integrated circuit in order to illustrate the method of an additional embodiment of the present invention.

#FIGS. 3A-3H are diagrammatic sectional views of an integrated ciecuit in order to illustrate the method of a further embodiment of the present invention.

#FIGS. 1A-1G illustrate the preferred embodiment of the present invention. On a suitable P- wafer 10 having a resistivity of 10 ohms/cm, an N+ region 11 which will subsequently serve as a buried subcollector is formed by conventional thermal diffusion of impurities as set forth for example in U.S. Pat. No. 3,539,876. When introduced into substrate 10, N+ region 11 has a surface concentration of 10.sup.21 atoms/cm.sup.3. Region 11 may also be formed by conventional ion implantation techniques. After the formation of region 11, N-type layer 12 is formed by epitaxial deposition in the conventional manner, e.g., the method described in U.S. Pat. No. 3,539,876. Epitaxial layer 12 has a maximum doping level of 1.times.10.sup.18 atoms/cm.sup.3. During the deposition of the epitaxial layer. buried N+ subcollector region 11 out-diffuses up into the epitaxial layer as shown in FIG. 1A. Then, as shown in FIG. 1A, a layer of silicon dioxide 13, 1600 .ANG. in thickness is formed in any conventional manner as described in the aforementioned patent, and openings 14 are selectively etched therein using conventional lithographic integrated circuit fabrication techniques. Then, P+ regions 15 are formed through the introduction of conductivity-determining impurities such as boron to a C.sub.0 of 2.times.10.sup.20 atoms/cm.sup.3 to produce the structure shown in FIG. 1B. The P-type impurities may be introduced either by diffusion or ion implantation. Next, P+ regions 15 are selectively etched away through the application of etchant through openings 14. In order to expedite the etching, advantage is taken of the property of anodic etching to selectively etched highly doped regions such as P+ region 15 at a higher rate than the adjacent layer 12 having a lower doping level. The anodic etching step may be carried out in any conventional anodic etching apparatus such as that described in the IBM Technical Disclosure Bulletin, Vol. 15, No. 2, July 1972, page 682, in an article by J. L. Deines. In the anodic etching, the anode positive voltage is applied to substrate 10 while a platinum foil in a 5% HF aqueous solution serves as the cathode. During the anodic etching, the electrolyte is maintained at a current density of 0.1 amp/cm.sup.2 and an applied voltage of six volts to produce recesses 16, FIG. 1C, extending to a depth of about 2 microns from the surface of silicon epitaxial layer 12 thereby extending through layer 12.

#Then, FIG. 1D, a layer of aluminum about 1.5 microns in thickness is deposited over the structure to produce the layer shown in FIG. 1D, wherein aluminum layers 17 fill in the order of 70% of recesses 16 while aluminum layer portions 18 are deposited on silicon dioxide surface layer 13. Aluminum layers 17 and 18 may be deposited by any conventional techniqu for forming aluminum metallurgy in integrated circuits, e.g., the standard vacuum deposition techniques utilized in the process of U.S. Pat. No. 3,539,876.

#Then, FIG. 1E, aluminum deposits 17 in recesses 16 are anodized to form aluminum oxide regions 18. The anodization of aluminum may be carried out in the conventional manner, i.e in a standard electrolytic solution. A typical process and apparatus for this anodization is described in Semiconductor Silicon, 1973, The Proceedings of the Electrochemical Society Conference at Chicago, May 13, 1973, in an article by D. K. Seto, pp. 651-657, particularly FIG. 1 thereof. Apparatus which may be utilized in this anodization process are also described in the IBM Technical Disclosure Bulletin, July 1972, in an article by J. L. Deines, pp. 682-683. The wafers are contacted at the back side of the substrate with a positive applied voltage of about 10 V. An eight per cent aqueous solution of sulfuric acid serves as the electrolyte, and a platinum foil cathode can be used as the counterelectrode. The applied voltage is maintained at a constant value during the ionization which is allowed to proceed until the current decays to a density of less than 0.02 milliamps/cm.sup.2.