Fault testing a clock distribution network
AssigneeInternational Business Machines Corporation
InventorsGregory S. Buchanan, John J. DeFazio
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AssigneeInternational Business Machines Corporation
InventorsGregory S. Buchanan, John J. DeFazio
Estimating the term…
A method and apparatus for fault testing a clock distribution network which provides a plurality of clock signal lines to the logic networks which comprise a data processor. The fault testing apparatus includes a decoder for selecting one of the clock signal lines to be tested, and a test latch which is clocked by the selected clock signal line. The selected clock signal line is tested by setting the test latch to a first logic value (e.g., binary ZERO) and maintaining a second logic value (e.g., binary ONE) at the test latch input. If the second logic value is stored in the test latch when the clock distribution network is inhibited, then a stuck-on fault is indicated for the selected clock signal line. If the second logic value fails to be stored in the test latch when the clock distribution network is enabled, then a stuck-off fault is indicated for the selected clock signal line. Each clock signal line in the clock distribution network may be tested in this manner.
A method of fault testing a clock distribution network which fans out a clock signal to a plurality of clock signal lines, by performing the following steps on a clock signal line:
A method of fault testing a clock distribution network which fans out a clock signal to a plurality of clock signal lines, by performing the following steps on a clock signal line:
A method of fault testing a clock distribution network which fans out a clock signal to a plurality of clock signal lines, by performing the following steps on a clock signal line:
Apparatus for fault testing a clock distribution network which fans out a clock signal to a plurality of clock signal lines, comprising:
A data processor comprising:
Dependencies are inferred from the claim text.