Arrangement for the synchronous demultiplexing of a time division multiplex signal
AssigneeSiemens Aktiengesellschaft
InventorsHeinrich Fladerer, Johann Magerl
Life of this patent
Estimating the term…
Abstract
A time division multiplex signal of a high order with a frame code word occurring as a block is distributed between a plurality of channels in a demultiplexer by way of a chain circuit of conductor elements. Further on the transmission path contains memories and a channel distributor. The channel distributor is controlled by a second memory by way of a decoder, other memories and a coder in a single step. A logic linking arrangement and a frame counter permit resynchronization only when the frame code word has failed to appear four times. The synchronous multiplexer facilitates high-speed operation at bit rates of 140 Mbit/s and 565 Mbit/s and likewise permits construction in accordance with emitter-coupled logic technology.
Claims16
An arrangement for synchronizing outgoing channels at the outputs of a demultiplexer by frame code words received as blocks in an incoming channel of a time-division multiplex system, comprising:
- a demultiplexer comprising an input for receiving the time-division multiplexed signal, a chain circuit connected to said input and including n-1 delay elements, each having a one bit delay of the time, and a plurality of taps including said input as a zero delay tap, and a first memory comprising n D flip-flops each including an input connected to a respective tap and an output defining a respective channel;
- a transmission path including an input connected to said outputs of said D flip-flops for receiving frame code words from said channels, an output for providing synchronized outgoing channels, a second memory connected to said input, a third memory connected to said second memory, a channel distributor connected to said third memory, and a fourth memory connected between said channel distributor and said outputs and
- a control path comprising a decoder connected to said second memory for decoding frame code words, a fifth memory connected to said decoder, a sixth memory connected to said fifth memory and including a switch through output, a logic linking arrangement connected to said fifth and sixth memories, for recognizing frame code words, a frame counter connected to said logic linking arrangement for counting frames and connected to said logic linking arrangement and to said sixth memory to cause switch through of a corresponding channel predetermined in response to the recognition of a number of frame code words, and a coder connected to said switch through output and to said channel distributor for causing synchronous distribution of the output channels via said fourth memory.
The arrangement of claim 14, wherein:
- said sixth memory comprises four channels each including a respective D flip-flop connected to said Q output of a corresponding D flip-flop of said third memory, and a clock input connected in common with the other D flip-flops of said sixth memory;
- and
- a fifth AND gate including an output connected to said clock inputs of said D flip-flops of said sixth memory, a first input connected to receive a clock pulse and a second input connected to receive a control pulse.
Dependencies are inferred from the claim text.