Interface for managing information exchanges on a communications bus
AssigneeCentre National De La Recherche Scientifique
InventorsJean Chevalet, Robert Reeves
Life of this patent
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AssigneeCentre National De La Recherche Scientifique
InventorsJean Chevalet, Robert Reeves
Estimating the term…
An interface for managing information exchanges on a communications bus between at least one control unit and peripheral units, or between said peripheral units. The exchanged information includes data and a destination address of said data. The interface is characterized in that it comprises for each unit, data transmission circuitry connected to the unit and to the bus for managing the data transmission on the bus to the unit having the destination address, data reception circuitry connected to the units and to the bus, for managing the reception of data by the unit having the destination address, and management circuitry for managing the addressing of the units during exchanges and in particular for managing access priorities to the bus, without necessitating the intervention of the control unit. This interface can be used for information exchanges between processing or measuring units.
An interface arrangement for managing the exchange of information between units connected by a communications bus, said units including at least one control unit and a plurality of peripheral units, each of said units having a distinct address, any one of said units being capable of transmitting and receiving information comprising data and a destination address, said destination address corresponding to the address of the one of said units which receives transmitted information wherein said interface arrangement comprises:
The interface arrangement as defined in claim 21, wherein said bus comprises a plurality of priority determination address lines, and said scanning means comprises a counting means connected to output said address signals to said plurality of priority determination address lines and a clocking means connected to output clocking signals to said counting means, wherein each of said predetermined sequence of address signals comprises a plurality of binary signals representing the increasing count carried out by said counting means.
Dependencies are inferred from the claim text.