Multiplexing and demultiplexing system with justification

A demultiplexing system with dejustification from high rate plesiochronous digital signals to convert them to a low rate synchronous digital signals, said demultiplexing system being associated with and receiving signals from a multiplexing system with justified conversion from low rate synchronous digital signals to high rate plesiochronous digital signals in response to a common justification circuit means having a bit insertion circuit with data inputs which are individually associated with outputs of a synchronization means to deliver a high rate justified plesiochronous digital signals responsive to a local clock source which is independent of said low rate synchronous digital signals insofar as jitter is concerned, said demultiplexing system comprising:

• a time base clock means, demultiplex means connected to receive signals from a high rate transmission line and a plurality of desynchronization means connected to transmit to a low rate transmission line, said demultiplexing system further including a common dejustification circuit means having a clock input connected to a corresponding output of the time base clock and an output which delivers write clock signals to said desynchronization means, justification indication read-out circuit means having a clock input connected to outputs of said demultiplexer means and to a control input of said common justification circuit means, data inputs of said desynchronization means being connected to outputs of the demultiplexer means, and said desynchronization means having read clock inputs connected to the output of the local clock source means.

A digital transmission terminal with justified two-way conversion between low rate synchronous digital signals and high rate plesiochronous digital signals, said system including digital send means and digital receive means;

• said send means comprising:
• time base clock circuit means, multiplexer means having an output coupled to a high rate plesiochronous line for transmission of digital signals at a nominal rate subject to natural deviation, a plurality of synchronization means respectively connected to receive signals from a low rate transmission line, common justification circuit means having write clock signals for supplying clock signals to said synchronization means, a common justification control circuit having a clock input connected to a corresponding output of the time base clock circuit means, common justification bit insertion circuit means, a control output being connected to a control input of the common justification circuit means and data output being connected to a control input of a common justification bit insertion circuit means, said bit insertion circuit means having data inputs which are individually associated with outputs of the synchronization means which deliver high rate plesiochronous digital signals, two input comparator means, local clock source means synchronized responsive to an applied low rate synchronous digital signals, the control input of the common justification control means being connected to the output of said comparator means, one input of said comparator means being connected to the output of the common justification circuit means and another input being connected to an output of said local clock source means, said local clock source means being independent of said low rate synchronous digital signals insofar as jitter is concerned;
• said receive means comprising:
• a time base clock means, demultiplex means connected to a high rate plesiochronous line for reception of digital signals at said nominal rate subject to said natural deviation and a plurality of desynchronization means connected to a low rate transmission line, said demultiplexing system further including a common dejustification circuit means having a clock input connected to a corresponding output of the time base clock and an output which delivers write clock signals to said desynchronization means, justification indication read-out circuit means having a clock input connected to outputs of said demultiplexer means and to a control input of said common justification circuit means, data inputs of said desynchronization means being connected to outputs of the demultiplexer means, and said desynchronization means having read clock inputs connected to the output of the local clock source means.