US 4,542,498 A · High bit-rate coupler between a PCM channel multiplex and a packet switching unit

Abstract

A high bit-rate coupler is connected between a PCM channel bidirectional multiplex and a packet switching unit. Each channel carries packet words, such as octets, grouped in frames separated by flags 01111110. The coupler processes the first level related to the bits of the frame level of a packet exchange procedure. For each received frame, the coupler extracts the filling zeros from the received words between the flags, controls a frame checking sequence included at the end of each frame, counts the realigned words without filling zeros to be transmitted to the switching unit, and detects the flags and the start and end of the frame. At the transmitting end, the coupler inserts filling zeros in each transmitted frame when it detects six contiguous bits "1" in the words delivered from the switching unit, derives the frame checking sequence, transmits the dealigned words with the filling words, and produces flags. The memory capacity of the coupler is reduced to the characteristics or contexts for processing a word in each channel. Processing means common to the packet mode channels processes progressively the received words and the transmitted words without storing of entire frames. A storing means of the coupler has as many memory cells as channels for storing in each cell the contexts written after a word of the respective channel has been processed, and read for the next word in the respective channel to be processed after the other channels have been processed, at the rate of one word per channel.

Claims11

Dependent claims

A coupler between a PCM channel bidirectional multiplex and a packet switching unit, the PCM channels carrying words with a predetermined number of bits and being multiplexed word by word, the PCM channels being multiplexed packet mode channels each carrying data word frames separated from each other by at least one flag and including filling bits having a first predetermined binary value such that said frame are without flags, said coupler comprising receiving means for extracting the filling bits from frames received from said multiplex and for supplying said received frames without said filling bits to said switching unit, and transmitting means for inserting said filling bits in transmitted frames derived by said switching unit and for supplying said transmitted frames with said filling bits to said multiplex, said receiving means and transmitting means each comprising:

logic means for processing only one channel word at a time to derive at least one portion of said channel word, the derived channel word portion being in the form of a word, and memory means having as many memory cells as the number of said channels for storing the contents of each channel in the cells, said contents of a word being written into the memory means after a word in a channel has been processed by the logic means and read from the memory means at a time to enable the next word in said channel to be processed by the logic means after the other channels have been processed by the logic means, the writing and reading being at the rate of one word per channel.

A coupler connected between a pulse code modulated multiplexed signal line and a packet circuit switching unit, the multiplexed signal having a first bit rate f and plural parallel channels at a second bit rate f/(n.sub.1) where n.sub.1 is a first integer, the channels being divided into frames at a third bit rate f/(n.sub.1 .multidot.n.sub.2), where n.sub.2 is a second integer, certain of the frames being high level data link packet frames, the high level data link packet frames including plural sequential words, each word including several sequential bits, the bits of the packet frame words being coded to represent addresses, control functions, information, and frame checking sequences, adjacent frames being separated by at least one flag representing word, the frames including filling bits having a predetermined value so that the frames contain no flag representing words, said coupler comprising:

receiving means responsive to the signal on the line for processing the signal supplied to the coupler and for coupling the processed signal to the coupler,
transmitting means responsive to a signal derived from the coupler and for processing the signal derived from the coupler so it is a pulse code modulated signal having bit rate f with plural channels at bit rate f/(n.sub.1) divided into frames at bit rate f/(n.sub.1 .multidot.n.sub.2),
the receiving means including means for extracting the filling bits from the signal supplied by the line to the coupler so the signal supplied by the coupler to the packet circuit switching unit has no filling bits,
the transmitting means including means for inserting filling bits into the signal supplied by the packet circuit switching unit to the coupler so the frames in the signal supplied by the coupler to the line have no flag words therein, the transmitting and receiving means each including high level data link processing logic circuitry for sequentially processing only one word of a channel at a time, memory means exchanging signals with an operating synchronously with the processing logic circuitry of the transmitting and receiving means, the memory means having plural sequentially addressed cells for storing the bits of a packet mode channel so that the memory means is organized to store the data by channel addresses and by frame addresses in the channels, means for cyclically reading bits of successive packet mode channel words from the memory during first successive intervals, means for cyclically writing bits of successive packet mode channel words into the memory during successive second intervals, each of the second intervals occurring between a pair of adjacent ones of the first intervals.

1 more element

Dependencies are inferred from the claim text.

High bit-rate coupler between a PCM channel multiplex and a packet switching unit

Life of this patent

High bit-rate coupler between a PCM channel multiplex and a packet switching unit

Life of this patent

Abstract

Claims11