US 4,542,483 AGranted

Dual stage sense amplifier for dynamic random access memory

AssigneeAT&T Bell Laboratories

InventorFrank J. Procyk

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Abstract

The present invention relates to the inclusion of an additional sense amplifier (100) on each column of a dynamic random access memory (RAM). The second sense amplifier is located near the input/output (DQ) line and functions to increase the rate of discharge of the selected column pair (C.sub.n, C.sub.n) thereby improving the transfer of logic information from a selected memory cell (M) to the input/output line associated therewith. The second sense amplifier in the column of the selected memory cell is activated by the same pulse (CCDQ) which connects the selected column to the input/output line, where only the second sense amplifier associated with the accessed column is activated during a single read/write cycle.

Claims8

Dependent claims

A random access memory device comprising

an array of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell comprising an information storage device, a row access port and a column access port;
a plurality of row access lines, each row access line coupled to the row access ports of a separate row of memory cells, for selecting a row of memory cells to be accessed by applying a row access signal to one row access line of said plurality of row access lines;
a plurality of column access line pairs, each pair of column access lines coupled to the column access ports of a separate column of memory cells, means for selecting a column of memory cells to be accessed, wherein the intersection of an accessed row and an accessed column pair define a selected memory cell;
a plurality of input/output lines disposed at one end of the random access memory device, each input/output line couplable to a separate one of the column access lines in each pair of column access lines, for either one of inputing logical information to and outputting logical information from, the selected memory cell;
a first plurality of sense amplifiers, each sense amplifier associated with a separate one of the pair of column access lines, located opposite to the plurality of input/output lines for sensing the logical information stored in the selected memory cell and restoring said logical information in said selected memory cell subsequent to being accessed;
and
a second plurality of sense amplifiers, each sense amplifier associated with a separate one of the pair column access lines, located adjacent to the plurality of input/output lines for sensing the presence of a column access signal and either one of quickly transferring the logic information stored in the selected memory cell to the input/output line and quickly transferring input logic information from the input/output line to the selected memory cell.

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Dependencies are inferred from the claim text.

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Abstract

A random access memory device comprising

an array of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell comprising an information storage device, a row access port and a column access port;
a plurality of row access lines, each row access line coupled to the row access ports of a separate row of memory cells, for selecting a row of memory cells to be accessed by applying a row access signal to one row access line of said plurality of row access lines;
a plurality of column access line pairs, each pair of column access lines coupled to the column access ports of a separate column of memory cells, means for selecting a column of memory cells to be accessed, wherein the intersection of an accessed row and an accessed column pair define a selected memory cell;
a plurality of input/output lines disposed at one end of the random access memory device, each input/output line couplable to a separate one of the column access lines in each pair of column access lines, for either one of inputing logical information to and outputting logical information from, the selected memory cell;
a first plurality of sense amplifiers, each sense amplifier associated with a separate one of the pair of column access lines, located opposite to the plurality of input/output lines for sensing the logical information stored in the selected memory cell and restoring said logical information in said selected memory cell subsequent to being accessed;
and
a second plurality of sense amplifiers, each sense amplifier associated with a separate one of the pair column access lines, located adjacent to the plurality of input/output lines for sensing the presence of a column access signal and either one of quickly transferring the logic information stored in the selected memory cell to the input/output line and quickly transferring input logic information from the input/output line to the selected memory cell.

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