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US 4,542,476 AGranted
Arithmetic logic unit
AssigneeHitachi, Ltd.
InventorMotonobu Nagafuji
Life of this patent
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Abstract
An arithmetic logic unit processes a variable operand length instruction such as a decimal arithmetic operation instruction, a plurality of bytes at a time using a multi-byte depth arithmetic operation unit. Multi-byte data including first and second operands are supplied to the arithmetic logic unit through a suppressing circuit. The suppressing circuit suppresses unnecessary bytes other than operand bytes and suppresses all of the bytes of one of the operands when the one operand has been exhausted.
Claims6
An arithmetic logic unit comprising:
- (a) data supplying means for supplying multi-byte depth data including first and second operands, respectively;
- (b) suppressing means for suppressing bytes other than operand bytes of the data supplied from said supplying means, said suppressing means including means for suppressing all of the multi-bytes of one of said operands when said one operand has been exhausted;
- (c) arithmetic logic means for simultaneously processing the multi-byte depth data supplied from said suppressing means;
- and
- (d) means responsive to an operation of said arithmetic logic means for updating an operand length specified by an instruction for each multi-byte depth processing operation to produce a signal indicating whether the operand has been exhausted or not in accordance with the updated operand length, said signal being supplied to said suppressing means, wherein said means for producing the signal indicating whether the operand has been exhausted or not responds to the change of said updated operand length to a negative value.
2 more elements
Dependencies are inferred from the claim text.