Burst mode data block transfer system
AssigneeBurroughs Corporation
InventorsDavid J. Mortensen, Jayesh V. Sheth
Life of this patent
Estimating the term…
Abstract
A data transfer system whereby a peripheral-controller manages data transfers between the host computer and a magnetic tape peripheral unit. Data undergoing transit, is temporarily stored in a buffer memory of the peripheral-controller and is monitored by a block counter monitoring system which informs a program-sequencer in the common control circuit unit of the peripheral-controller when data may be shifted into or out of the buffer memory in order to avoid or reduce the probability of access error conditions.
Claims8
A system for minimizing access errors during data transfer operations between a magnetic tape peripheral unit and a main host computer, wherein a peripheral-controller is initiated by instructions from said main host computer to manage data transfer operations between said host computer and said tape peripheral unit, and wherein said peripheral-controller includes a common front end circuit with a microprocessor unit for sequencing microcode instructions and a peripheral dependent circuit unit for interfacing said magnetic tape peripheral unit, the combination comprising:
- (a) common control circuit means including:
- (a1) microprocessor unit means for executing data transfer instructions in accord with commands received from said host computer, and including:
- (a1a) sensing means, connected to a memory status logic means in said peripheral dependent circuit unit, to receive status signals representing the number of blocks of data residing in a RAM buffer memory means;
- (a1b) means for executing data transfers in a burst mode or a demand mode according to the said status signals, said burst mode operating to transfer a block of N words per one instruction without interrupting said microprocessor unit means, and said demand mode operating to transfer individual bytes of one word for each instruction from said microprocessor unit means;
- (a1c) whereby said access errors are minimized by allocating sufficient time for transferring blocks of N words without interrupting the microprocessor in the burst mode and by allocating sufficient time for transferring individual bytes of a word in the demand mode means for addressing word storage areas of a RAM buffer memory means;
- (a2) RAM buffer memory means having data bus connections to said host computer and also to said tape peripheral unit, said memory means including:
- (a2a) multiple storage areas, each storage area providing a block of N words;
- (b) said peripheral dependent circuit unit connected to said common control circuit means and including:
- (b1) said memory status logic means for receiving address data to count words entering or leaving said RAM buffer memory means and including:
- (b1a) count logic means to maintain a count of the number of data blocks residing in said RAM buffer memory means, said count logic means providing a memory status signal to said microprocessor unit sensing means;
- (c) and wherein said microprocessor unit means will initiate burst mode data transfer operations from said RAM buffer memory means to said host computer only when at least B.sub.x full data blocks reside in said RAM buffer memory means awaiting transfer to said host computer, where B.sub.x is an integer equal to 2 or greater.
Dependencies are inferred from the claim text.