Apparatus for controlling access to a memory
AssigneeAdvanced Micro Devices, Inc.
InventorsJoseph A. Brcich, Roy J. Levy, Jimmy Madewell, N. Bruce Threewitt
Life of this patent
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Abstract
A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation.
Claims5
A controller for accessing a dynamic memory having a plurality of banks, and a plurality of rows and a plurality of columns for each of the plurality of banks, the memory storing data which are subject to being refreshed and to data bit errors, said controller having a read/write mode, a refresh mode and a refresh with error detection and correction mode, comprising:
- (a) a latch for storing first address data for addressing the memory for the read/write mode, the first address data having a first row address portion, a first column address portion and a first bank address portion;
- (b) an address counter for generating second address data for addressing the memory for the refresh mode and the refresh with error detection and correction mode, the second address data having a second row address portion, the second column address portion and a second bank address portion;
- (c) means for carrying a row address strobe input, a column address strobe input, a mode control input identifying any one said mode and a multiplexer select input;
- (d) multiplexer means, responsive to said mode control input and said multiplexer select input, for outputting to the memory the first row address portion and the first column address portion for the read/write mode or the second row address portion and the second column address portion for the refresh mode or the refresh with error detection and correction mode;
- (e) row address strobe decoder means, responsive to said first bank address portion, said mode control input and said row address strobe input, for producing and outputting to the memory any one of a plurality of row address strobe signals for the read/write mode and for producing and simultaneously outputting all of the plurality of row address strobe signals for the plurality of banks, respectively, for the refresh mode and for the refresh with error detection and correction mode;
- (f) column address strobe decoder means, responsive to said first bank address portion, said second bank address portion, said mode control input and said column address strobe input, for producing and outputting to the memory any one of a plurality of activating column address strobe signals for the read/write mode and the refresh with error detection and correction mode and deactivating the column address strobe signals for the refresh mode;
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- (g) timing means for monitoring the activity of control signals for the dynamic memory and connected to said mode control input for generating mode control signals to said mode control input in response to the activity of the control signals to dynamically select any one said mode.
Dependencies are inferred from the claim text.