Manchester decoder

A decoder for Manchester encoded data signals, the binary data of which is included in Manchester bit cells with each Manchester bit cell being divided into two half-bit cells, the binary data of the cell being determined by the voltage level transition occurring between two half-bit cells, comprising:

• an EXCLUSIVE-OR gate for producing a primary pulse, said EXCLUSIVE-OR gate having two input terminals;
• circuit means for applying the data signals directly to one input terminal of the EXCLUSIVE-OR GATE MEANS;
• circuit means including a delay circuit for applying the data signals to the other input of the EXCLUSIVE-OR gate means;
• a delay line oscillator means having an enable terminal for producing a square wave decode clock signal when enabled;
• circuit means for applying the output of the EXCLUSIVE-OR gate to the enable terminal of the delay line oscillator;
• a decoder shift register having a clock input terminal, a master reset input terminal, and "n" output terminals where "n" is an integer other than zero;
• inverter circuit means for applying the output of the EXCLUSIVE-OR gate means to the master reset input terminal of the decoder shift register;
• circuit means for applying the square wave decode clock signal produced by the delay line oscillator to the clock terminal of the decoder shift register;
• logic circuit means to which the primary pulse and selected ones of the output terminals of the decoder shift register are applied for producing a receive clock signal, said receive clock signal having a voltage transition of one type substantially in the center of each half-bit cell of the data signal;
• a receive data serial in parallel out shift register having a clock input terminal and a data input terminal;
• circuit means for applying the data signals to the data input terminal of the receive data shift register;
• and
• circuit means for applying the receive clock signal to the clock terminal of the receive data shift register to shift the voltage levels of each half-bit cell of a Manchester bit cell into the receive data shift register with the voltage level so shifted being substantially from the middle of each half-bit cell of a Manchester bit cell.