US 4,542,351 AGranted

PLL for regenerating a synchronizing signal from magnetic storage

AssigneeFujitsu Limited

InventorToshiro Okada

Life of this patent

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Abstract

A phase-locked loop circuit, which obtains a signal synchronized with a phase of an input signal, including a synchronizing portion, and a data portion having a voltage controlled oscillator, a frequency phase comparator, a phase comparator, and a control circuit. The frequency phase comparator detects the phase difference and the frequency difference between the input signal and the output of the voltage controlled oscillator and the phase comparator detects the phase difference between the input signal and the output of the voltage controlled oscillator. The control circuit controls the voltage controlled oscillator, at least during a portion of the synchronizing signal portion, in accordance with the output of the frequency phase comparator, and, during the data signal portion, in accordance with the output of the phase comparator.

Claims7

Dependent claims

A phase-locked loop circuit for receiving an input signal and providing a signal synchronized with the input signal, the input signal having a synchronizing signal portion formed by a constant frequency signal and a data signal portion formed by a non-constant frequency signal, said phase-locked loop circuit comprising:

a reference frequency signal generator for generating a reference frequency signal;
a voltage controlled oscillator for outputting an output signal which functions as a clock signal;
frequency phase comparing means, operatively connected between said voltage controlled oscillator and said reference frequency signal generator, for detecting the frequency difference and the phase difference between the reference frequency signal and the output signal of said voltage controlled oscillator and outputting a first output signal;
phase comparing means, operatively connected to receive the clock signal and the input signal, for detecting the phase difference between the input signal and the clock signal and outputting a second output signal;
first controlling means, operatively connected between said frequency base comparing means and said voltage controlled oscillator, for generating a first controlling signal for controlling said voltage controlled oscillator during at least a portion of the synchronizing signal portion of the input signal, the first controlling signal generated in accordance with the first output signal of said frequency phase comparing means;
second controlling means, operatively connected between said phase comparing means and said voltage controlled oscillator, for generating a second controlling signal for controlling said voltage controlled oscillator during the data signal portion, the second controlling signal generated in accordance with the second output signal of said phase comparing means, the first and second controlling signals being combined to generate an input control signal, the input control signal controlling the oscillation frequency of the voltage controlled oscillator.

3 more elements

A phase-locked loop circuit for providing a signal synchronized with a phase of a data signal having a portion including synchronizing bits and having a portion including data bits, comprising:

reference frequency signal means for providing a reference signal;
frequency phase comparing means, operatively connected to the reference frequency signal means and operatively connected to receive a voltage controlled signal, for comparing the reference signal with the voltage controlled signal and outputting a first control signal;
phase comparing means, operatively connected to receive the data signal and a frequency signal, for outputting a second control signal;
control means, operatively connected to said frequency phase comparing means, for receiving the first and second control signals output from said frequency phase comparing means and said phase comparing means, respectively, and outputting an output control signal;
a voltage controlled oscillator, operatively connected to said control means and said frequency phase comparing means, for receiving and being controlled by the output control signal and outputting the voltage controlled output signal in accordance with the portion including data bits and the output control signal;
dividing means, operatively connected to receive a clock signal, for providing the frequency signal, which is one-half the frequency of the voltage control output signal, to said frequency phase comparing means and said phase comparing means;
and
a synchronous pattern detection circuit, operatively connected to receive the data signal and operatively connected to said control means, for counting synchronizing bits in the synchronizing signal portions and controlling said control means in accordance with a predetermined number of counted bits.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/415,797Filed 8 Sep 1982
Priority: JP 57-288048 Sep 1981
Granted: 17 Sep 1985
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03L 7/14
Details of the phase-locked loop: for assuring constant frequency when supply or correction voltages fail
G11B 20/1403
Using self-clocking codes: characterised by the use of two levels
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L 7/113
For assuring initial synchronisation or for broadening the capture range: using frequency discriminator