Back to results
US 4,542,306 AGranted
Buffer circuits for use with semiconductor memory devices
AssigneeNippon Electric Co., Ltd.
InventorHiroaki Ikeda
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNippon Electric Co., Ltd.
InventorHiroaki Ikeda
Estimating the term…
In a buffer circuit for producing two output signals of the opposite phases in response to an input signal comprising a pre-circuit producing two pre-output signals in accordance with the input signal and a reference voltage signal; and a main circuit including a latch circuit latching the pre-output signals, and a flip-flop circuit connected to receive the pre-output signals latched by the latch circuit for producing the output signals of the buffer circuit, there is provided a transfer gate circuit enabled by the pre-output signals and disabled by the output signals of the buffer circuit. According to this invention, different from the prior art circuit, it is not necessary to use any clock signal having a high level at the time of operation of the buffer circuit and to have strict time spacing, whereby the clock signal generator can be simplified and the buffer circuit can be miniaturized and its operating speed can be increased.
In a buffer circuit for producing two output signals of opposite phases in response to an input signal comprising a pre-circuit producing two pre-output signals in accordance with said input signal and a reference voltage signal;
A buffer circuit comprising first and second input nodes, a flip-flop circuit having first and second input/output nodes, means for operatively charging said first and second input/output nodes with a predetermined potential, a first series circuit of the drain-source current paths of first and second field effect transistors, a second series circuit of the drain-source current paths of third and fourth field effect transistors, said first series circuit being connected between said first input node and said first input/output node, said second series circuit being connected between said second input node and said second input/output node, means for connecting the gates of said first and fourth transistors to said first input/output node, and means for connecting the gates of said second and third transistors to said second input/output node.
Dependencies are inferred from the claim text.