Clock pulse generating circuit

A clock pulse generating circuit for producing multiphase clock pulses, comprising;

• an input terminal for being supplied with an input signal containing a pulse;
• first and second clocking terminals for delivering first and second timing signals, respectively, each of said first and second timing signals being composed of pulses having a constant cyclical period and a period of each pulse of first timing signal being not coincident with a period of each pulse of said second timing signal without overlapping to each other;
• plural first circuit blocks each comprising a first switching element being supplied with said first timing signal, a first capacitive element coupled in series with said first switching element, and a NOR gate circuit connected to be supplied with said first timing signal and a voltage obtained at the connecting point between said first switching element and said first capacitive element;
• and
• plural second circuit blocks each connected between each successive two of said first circuit blocks to form a series multistate configuration and each comprising a second switching element being supplied with said second timing signal, a second capacitive element coupled in series with said second switching element, and an inverter connected to be supplied with a voltage obtained at the connecting point between said second switching element and said second capacitive element, said second switching element being also connected to the output end of the NOR gate circuit in one of successive two of said first circuit blocks and the output end of the inverter is connected to the first switching element in the other of said successive two of said first circuit blocks;
• wherein said input signal is supplied to the first switching element in the first one of said first circuit blocks with a pulse period greater than one cyclical period of said first timing signal and output signals are derived from the NOR gate circuits in said first circuit blocks.