Process for fabricating pedestal interconnections between conductive layers in an integrated circuit

Abstract

A process for fabricating pedestal interconnections between conductive layers in an integrated circuit includes the steps of (a) forming a first conductive layer over a semiconductor substrate; (b) applying a stop etch layer to said first conductive layer, the stop etch layer having a different etch property than the first conductive layer; (c) patterning the first conductive layer and the stop etch layer in an interconnection pattern which includes widened regions wherever a pedestal interconnection is to be formed; (d) selectively etching the stop etch layer until the stop etch layer remains as a stop etch cap only in central sections of the widened regions; and (e) selectively etching the first conductive layer to a selected depth whereby a pedestal is formed underneath the stop etch caps. The following optional steps may be added: (f) applying a layer of an insulating material over the first conductive layer; and (g) planarizing the insulating layer to expose the tips of the pedestals.

Dependencies are inferred from the claim text.