Pattern processing system

A method of associating an input pattern with an output response, wherein the input pattern comprises a plurality of sample values, the method comprising:

• periodically storing the sample values of the input pattern at a first rate in a first array of addressable locations;
• sequentially addressing the first array at a second higher rate with a sequence of addresses in which each next address of the sequence is determined by a preceding address of the sequence and the sample value stored at the addressable location of the first array corresponding to the preceding address, so that a repetitive address loop which is a function of the input pattern is generated as long as the input pattern remains unchanged;
• and
• associating the output response with the address loop which is a function of the input pattern.

A pattern processing system for identifying an input pattern comprising:

• addressable means for providing, for each of a plurality of addressable locations, a sample value representative of a characteristic of an input pattern at that addressable location;
• address sequencer means for providing an address stream containing a sequence of addresses in which each next address of the sequence is determined by a preceding address and the sample value from the location corresponding to the preceding address;
• so that upon repetition of an address which has previously been provided in the sequence, the address stream cycles repetitively through an address loop which is a function of the input pattern for as long as the input pattern remains unchanged;
• and
• means responsive to the address stream for identifying the input pattern based upon the address loop which it causes to be provided by the address sequencer means.

A pattern processing system for identifying combinations of first and second input patterns, the system comprising:

• first addressable means for providing first sample values representative of the first input pattern at a plurality of addressable locations;
• second addressable means for providing second sample values representative of the second input pattern at a plurality of addressable locations;
• first address sequencer means for providing a first address stream to the first addressable means, the first address stream containing a sequence of addresses in which each next address of the sequence is determined by a preceding address and the first sample value from the location corresponding to the preceding address;
• second address sequencer means for providing a second address stream to the second addressable means, the second address stream containing a sequence of addresses in which each next address of the sequence is determined by a preceding address and the second sample value from the location corresponding to the preceding address;
• and
• means for identifying combinations of the first and second input patterns based upon the first and second streams.

A pattern processing system comprising:

• first addressable means for storing at a plurality of addressable locations sample values representative of an input pattern during a first temporal interval;
• first address sequencer means for providing a first address stream containing a sequence of addresses in which each next address of the sequence is determined by the preceding address and the first sample value from a location of the first addressable means corresponding to the preceding address, so that upon repetition of an address which has previously been provided in the sequence, the address stream cycles repeatedly through an address loop which is a function of the input pattern;
• second addressable means for storing at a plurality of addressable locations an array of second sample values representative of addresses contained in the first address stream during a second temporal interval which includes a plurality of first temporal intervals;
• second address sequencer means for providing a second address stream containing a sequence of addresses in which each next address of the sequence is determined by a preceding address and the second sample value from the location corresponding to the preceding address, so that upon repetition of an address which has previously been provided in the sequence, the address stream cycles repetitively through an address loop which is a function of the array of second samle values;
• and
• means responsive to the second address stream for identifying the input pattern during the second temporal interval based upon an address loop contained in the second address stream.

A pattern processing system for identifying a pattern, the system comprising:

• means for generating an address stream containing at least one sequence of addresses in which each next address of the sequence has a plurality of possible next address values based upon at least one preceding address, and wherein the next address is selected from among the possible next address values based upon at least one sample value related to the one preceding address so that at least one repetitive address loop which is a function of the pattern is generated;
• means for providing, in response to each address of the address stream, a sample value representative of a characteristic of a sampled element of a pattern corresponding to that address;
• and
• means for identifying the pattern based upon the sequence of addresses generated when the pattern is sampled as a function of addresses of the address stream.

A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response, the system comprising:

• buffer means for storing the sample values of the input pattern in a first array of addressable locations;
• response memory means for storing codes in a second array of addressable locations;
• address sequencer means for providing a sequence of addresses, a next address of the sequence being determined by a preceding address and the sample value stored by the buffer means at the location corresponding to the preceding address;
• so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern;
• training controller means for selectively causing a predetermined code associated with the input pattern to be written into the response memory means at locations of the second array determined by the addresses of an address loop produced when the input pattern is stored by the buffer means and addressed by the address sequencer means;
• and
• response detector means for providing the output response based upon codes read out from locations of the second array addressed by the sequence of addresses provided by the address sequencer means.

A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response during a training mode and subsequently providing the output response when the input pattern is present during a subsequent identifying mode, the system comprising:

• means for storing sample values of the input pattern in a first array of addressable locations;
• means for storing codes in a second array of addressable locations;
• means for providing a sequence of addresses corresponding to addressable locations of the first and second arrays, a next address of the sequence being determined by a preceding address of the sequence and the sample value stored at the location at the first array corresponding to the preceding address;
• so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern and which includes a plurality of addresses, as long as the input pattern remains unchanged;
• means for causing a predetermined code representative of the output response to be stored at selected locations of the second array determined by the addresses of the address loop produced during the training mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses;
• and
• means for providing the output response based upon the codes read out from locations of the second array addressed by the sequence of addresses generated during the identifying mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses.

A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response, the system comprising:

• buffer means for storing the sample values of the input pattern in a first array of addressable locations, the sample values stored being updated at a first rate;
• response memory means for storing codes in a second array of addressable locations;
• address sequencer means for providing a sequence of addresses at a second rate which is greater than the first rate, a next address of the sequence being determined by a preceding address and the sample value stored by the buffer means at the location corresponding to the preceding address;
• so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern;
• training controller means for selectively causing a predetermined code associated with the input pattern to be written into the response memory means at locations of the second array determined by the addresses of an address loop produced when the input pattern is stored by the buffer means and addressed by the address sequencer means;
• and
• response detector means for providing the output response based upon codes read out from locations of the second array addressed by the sequence of addresses provided by the address sequencer means.

A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response during a training mode and subsequently providing the output response when the input pattern is present during a subsequent identifying mode, the system comprising:

• means for periodically storing, at a first rate, sample values of the input pattern in a first array of addressable locations;
• means for storing codes in a second array of addressable locations;
• means for providing a sequence of addresses corresponding to addressable locations of the first and second arrays at a second rate which is greater than the first rate, a next address of the sequence being determined by a preceding address of the sequence and the sample value stored at the location at the first array corresponding to the preceding address;
• so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern and which includes a plurality of addresses, as long as the input pattern remains unchanged;
• means for causing a predetermined code representative of the output response to be stored at selected locations of the second array determined by the addresses of the address loop produced during the training mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses;
• and
• means for providing the output response based upon the codes read out from locations of the second array addressed by the sequence of addresses generated during the identifying mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses.