Self-checking computer circuitry

Circuitry for a fault-tolerant computer system comprising,

• two identical circuit halves, each of said circuit halves in turn comprising,
• a data processing and control unit capable of generating timing, addressing and control signals and generating and receiving data words of width N;
• a memory unit capable of storing data words of width less than N, said memory being responsive to said address signals for retrieving or storing data words therein;
• first means responsive to said control signals for transferring a portion of width less than N of said data words of width N between said data processing and control unit and said memory;
• second means responsive to said control signals for transferring data words of width less than N between said data processing and control unit and the memory in the other circuit half;
• interface means for connecting said circuit half to said computer system, said interface means being capable of handling data words of width less than N and being responsive to said control signals for passing data words of width less than N between said computer system and said first transferring means;
• means for comparing address information and data generated by said data processing and control unit with address information and data generated by the data processing and control unit in the other circuit half;
• means responsive to data words generated by said data processing and control means for encoding said data words generated by said data processing and control means with an error-detecting code;
• and
• means responsive to incoming information passing through said interface means for checking said error detecting code associated with said incoming information to insure proper reception of said information.

A circuit element for use in a fault-tolerant computer system comprising,

• a first circuit half, comprising,
• a first data processing and control unit capable of generating first timing, addressing and control signals and generating and receiving data words, said data words being comprised of a first data portion and a second data portion;
• a first memory unit responsive to said first timing, addressing and control signals for storing said first data portion;
• and
• a first interface responsive to said first timing, addressing and control signals for transferring said first data portion between said first circuit half and said computer system;
• a second circuit half, comprising,
• a second data processing and control unit capable of generating second timing, addressing and control signals and generating and receiving said data words;
• a second memory unit responsive to said second timing, addressing and control signals for storing said second data portion;
• a second interface responsive to said second timing, addressing and control signals for transferring said second data portion between said second circuit half and said computer system;
• and
• an address comparator means for comparing said first addressing signals with said second addressing signals.