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US 4,541,090 AGranted
Semiconductor memory device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorTsuyoshi Shiragasawa
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Abstract
A large capacity memory is improved so as to reduce its testing time length. Memory arrays are divided into a plural number of memory blocks having common address signal lines and common input/output lines, each memory block is provided with respective comparators thereby enabling testings of the plural number of memory blocks parallelly at the same time.
Claims6
A semiconductor memory device including a testing arrangement therein and adapted such that parts thereof tested as defective can be disabled, allowing those parts tested non-defective to be used, comprising:
- a plural number of memory array blocks having common address signal lines and common input/output lines,
- means for inputting predetermined data to predetermined addresses of said blocks:
- means for reading data previous input to said blocks as output data;
- a comparator associated with each block for said input and output data and providing a pass or fail signal indicative of an identity or non-identity, respectively therebetween and
- means for disabling any blocks for which a fail signal was provided by its associated comparator.
2 more elements
Dependencies are inferred from the claim text.