Memory using multiplexed row and column address lines
AssigneeAT&T Bell Laboratories
InventorsAustin C. Dumbri, Frank J. Procyk
Life of this patent
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Abstract
A memory of rows and columns of memory cells uses a multiplexed input address buffer having output row-column address lines which are coupled to a multiplexer and to column decoders. The multiplexer is coupled to row address decoders and serves to selectively couple the address lines to the row decoders. The address lines typically first carry row address information and then column address information. The use of a common portion of the address lines to couple the address buffer to the column decoders and multiplexer tends to reduce the overall size of the memory and thereby increases yield and reduces cost.
Claims11
A memory array of rows and columns of memory cells with row decoders coupled to the rows and column decoders coupled to the columns comprising:
- address lines coupled to the column decoders;
- a multiplexer coupled to the address lines and to the row decoders for selectively coupling the address lines to the row decoders;
- and
- portions of the address lines which are coupled to the multiplexer also being coupled to the column decoders,
- wherein:
- the memory array comprises an upper section and a lower section;
- the row decoders have an upper portion and a lower portion;
- the upper section of the memory array being separated essentially at the center into left and right-hand portions by the upper portion of the row decoders;
- the lower section of the memory array being separated essentially at the center into left and right-hand portions by the lower portion of the row decoders;
- the column decoders having left and right-hand portions;
- the left-hand portion of the column decoders being located between the upper and lower left-hand portions of the memory array;
- the right-hand portion of the column decoders being located between the upper and lower right-hand portions of the memory array;
- and
- the common portion of the address lines running between the upper and lower left-hand portions of the memory array,
- wherein:
- the multiplexer comprises a plurality of first switching devices which each have a control terminal and first and second output terminals;
- the control terminals of the switching devices all being coupled together to means for turning on or turning off all of the switching devices;
- and
- the first output terminal of each switching device being coupled to a separate one of the address lines and the second output terminal of each switching device being coupled through a separate row address line to a separate one of input terminals of the row decoders.
A memory array of rows and columns of memory cells with row decoders coupled to the rows and column decoders coupled to the columns comprising:
- address lines coupled to the column decoders;
- a multiplexer coupled to the address lines and to the row decoders for selectively coupling the address lines to the row decoders;
- portions of the address lines which are coupled to the multiplexer also being coupled to the column decoders;
- the memory array comprises an upper section and a lower section;
- the row decoders have an upper portion and a lower portion;
- the upper section of the memory array being separated essentially at the center into left and right-hand portions by the upper portion of the row decoders;
- the lower section of the memory array being separated essentially at the center into left and right-hand portions by the lower portion of the row decoders;
- the column decoders having left and right-hand portions;
- the left-hand portion of the column decoders being located between the upper and lower left-hand portions of the memory array;
- the right-hand portion of the column decoders being located between the upper and lower right-hand portions of the memory array;
- the common portion of the address lines running between the upper and lower left-hand portions of the memory array;
- the multiplexer comprises a plurality of first switching devices which each have a control terminal and first and second output terminals;
- the control terminals of the switching devices all being coupled together to means for turning on or turning off all of the switching devices;
- and
- the first output terminal of each switching device being coupled to a separate one of the address lines and the second output terminal of each switching device being coupled through a separate row address line to a separate one of input terminals of the row decoders.
Dependencies are inferred from the claim text.