Self compensating ROM circuit
AssigneeNational Semiconductor Corporation
InventorA. Karl Rapp
Life of this patent
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Abstract
A compensation arrangement is shown for the diffused column line resistance in an N channel metal gate read only memory. The circuit employs a dummy column which has a transistor at each possible location operated from the same decoder that operates the metal gate rows. A current sense circuit clamps the column pull-up end of the dummy column line and provides a correction signal that is fed to the pull-up devices in the memory columns. A second current sense circuit clamps the dummy column sense amplifier end of the column line and provides a correction signal that can be used to compensate the reference currents in column sense amplifiers using differential current sensing.
Claims10
In an MOS ROM integrated circuit memory chip having a memory section in which a plurality of transistors are located in an array of columns and rows, each of said columns including a pair of flanking diffused column lines and each of said rows including a metal transistor gate line, wherein said memory section includes an active transistor where a digital one is to be read out and an inactive or absent transistor where a digital zero is to be read out, and a peripheral section in which the circuits necessary to address and read said memory section are contained, the improvement comprising:
- a dummy column created from a representative one of said columns;
- an active transistor located at each memory location is said dummy column;
- means for selectively energizing each transistor in said dummy column in a sequence that is the same as that employed in the rows in said memory section;
- peripheral section circuitry coupled to said dummy column and responsive to said energizing sequence to generate a correction response signal related to the performance of said dummy column;
- and
- means for coupling said correction response signal to that portion of said peripheral section circuitry associated with said memory section columns whereby said memory section columns are compensated by said dummy column.
Dependencies are inferred from the claim text.