US 4,541,076 AGranted

Dual port CMOS random access memory

AssigneeStorage Technology Corporation

InventorsStephen G. Bowers, Tim B. Trueblood, Anthony Cabiedes

Life of this patent

Estimating the term…

Loading patent…

Abstract

A CMOS static RAM and CMOS logic gate array are combined on a single substrate to form a new CMOS logic masterslice. The RAM includes dual port capability whereby two independent address and data paths access a common memory cell. The logic gate array includes a large number of logic blocks that may be selectively customized to provide system needed logic functions. Two metal interconnect layers are employed to provide the desired interconnections between the RAM and gate array elements. In a preferred embodiment, the masterslice contains a 128.times.9 dual port static RAM, 586 blocks of gate array logic (each block being the equivalent of two-2 input logic gates), 96 I/O pads, and 8 power pads. In this embodiment, the masterslice may be realized on a substrate having a size of approximately 5.8 mm by 6.05 mm, and exhibiting typical address access times of 20 ns and write pulse widths of less than 15 ns.

Claims1

Dependent claims

A dual port CMOS random access memory comprising:

a memory array comprising a plurality of memory cell columns, each column being comprised of a plurality of memory cells;
two independent data ports coupled to each memory cell, each data port including a pair of data-in lines and a data-out line through which data may independently be written into or read from an address memory cell at a desired data rate;
two independent address means for respectively directing data through said data ports to or from a desired memory cell in response to address signals;
each memory cell column including two pairs of differential bit lines, one pair of bit lines being selectively coupled to said pair of data-in lines of one port, said coupling being realized with a first set of CMOS transfer gates responsive to said address means, the other pair of bit lines being selectively coupled to said pair of data-in lines of the other port, said coupling being realized with a second set of CMOS transfer gates responsive to said address means, each memory cell of said column being selectively coupled to said pairs of bit lines;
and
each memory cell column further including two sense amplifiers, each one of which is coupled to the pair of bit lines associated with one of said dual ports, said coupling occurring at a point between said first and second sets of CMOS transfer gates, the output of said sense amplifier being coupled to the data-out line of its respective port;
whereby two different memory cells may be accessed simultaneously at the same or at different data rates.

4 more elements

Dependencies are inferred from the claim text.