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AssigneeNEC Corporation
InventorKenji Ohmori
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A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.
A dynamic gate array for simulating an overall operation carried out by a combination of logic groups on a primitive signal to provide a derived signal, said logic groups being responsive to input signals for providing output signals, respectively, and being operable in steps in response to said primitive signal given as a particular one of said input signals to eventually provide a specific one of said output signals as said derived signal, said dynamic gate array comprising:
Dependencies are inferred from the claim text.