Reducing noise in introducing bias charge into charge transfer devices
AssigneeRCA Corporation
InventorJohn R. Tower
Life of this patent
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Abstract
A bias charge (commonly known as a "fat zero") is divided into a plurality, n, of equal parts. These equal parts are differentially delayed, and the results appearing parallel in time are summed to generate a bias charge with reduced noise. The reduced-noise bias charge is then applied to an input of a charge transfer device -- e.g., one of the charge coupled device (CCD) analog shift registers used in a CCD imager to transport charge packets descriptive of picture elements in an imager.
Claims14
Apparatus for generating reduced-noise bias charge packets for introduction into an input of a charge transfer device, which apparatus comprises:
- means for establishing a bias voltage level;
- a fill-and-spill input stage for periodically supplying, from its output, bias charge packets of a size responsive to bias voltage level applied to its input;
- a plurality, n in number, of charge transfer channels consecutively ordinally numbered first through nth, each charge transfer channel providing a delay between its input and output equal to the periodicity of successive fill-and-spill cycles multiplied by one less than the cardinal number corresponding to the ordinal numbering of that charge transfer channel;
- a charge splitter for equally apportioning charge packets received at its input from the output of said fill-and-spill input stage for application from respective outputs thereof to each of the inputs of said charge transfer channels;
- and
- means for summing the charge packets that appear parallel in time at the outputs of said charge transfer channels, to generate said reduced-noise bias charge packets.
A method for reducing the noise associated with the introduction of periodically generated bias charge packets into a charge transfer device, which method comprises the steps of:
- dividing each said periodically generated bias charge packet into a number n of parts, successively ordinally numbered first through n.sup.th, n being a plural integer;
- differentially delaying each of the parts relative to the others so they are respectively delayed by different numbers of periods and summing the differentially delayed parts that appear parallel in time to provide a reduced-noise bias charge packet each period;
- and
- applying the reduced-noise bias charge packets as bias charge to an input of said charge transfer device, rather than applying said periodically generated bias charge packets directly to said input of said charge transfer device.
A CCD time-domain filter comprising:
- a charge splitter receptive of an input charge for dividing said charge into a multiplicity of portions, the number of portions being at least m, an integer larger than two;
- a multiplicity, m, of charge transfer channels, at least two of which provide between a respective input and output of each different numbers of charge-transfer cycles of delay than each remaining one of those charge transfer channels provides between its input and output, said charge transfer channels
- having respective inputs receptive of different portions of said divided input charge and having respective outputs;
- and
- means for summing the charges from the outputs of said charge transfer channels to provide the output from said CCD time-domain filter.
Dependencies are inferred from the claim text.