Modular programmable signal processor

An arithmetic element responsive to a source of coefficients providing each coefficient during a first and a second clock period, to a source of control data provided during each clock period and to a source of data providing first and second words during respective first and second clock periods comprising:

• multiplier means coupled to said source of coefficients, to said source of control data and to said first and second words of said source of data;
• first and second arithmetic logic units coupled in parallel to the output of said multiplier means, said first and second arithmetic logic units also being coupled to said source of coefficients and to said source of control data;
• and
• one clock period delay mens coupled between said source of control data and said second arithmetic logic unit, said second arithmetic logic unit performing the same arithmetic function as said first arithmetic logic unit except delayed one clock period.

A processing system operable with control element means and external device means comprising:

• arithmetic element controller means for providing common control signals, common addresses and common coefficient data;
• an external interface unit coupled to said control element means and external device means, said external interface unit also coupled to said arithmetic element controller means for receiving selected ones of said common addresses;
• a plurality of arithmetic element means each including a work store unit for storing a block of data and each coupled to be responsive to said common addresses and said common control signals, calculating means coupled to said work store unit and responsive to saaid common control signals and said common coefficient data, and a limiter coupled to said calculating means and to said work store unit for providing data thereto, each arithmetic element means performing the same functional operation during the same time period;
• and
• a plurality of extended work store units each storing a block of data and each coupled to the calculating means of a associated one of said plurality of said arithmetic element means for transferring data to said calculating means, the limiter of each arithmetic element means coupled to the associated extended work store unit for transferring data thereto, each extended work store unit coupled to said external interface unit for responding to the selected common addresses and coupled to said arithmetic element controller means for responding to the same control signals so that all simultaneously perform the same reading and writing function during the same time period.

A processor system for operating with control element means and external device means comprising:

• arithmetic element controller means including a program memory for providing common control signals, an address generator for providing first and second common extended work store address signals and first and second common work store address signals and a coefficient store unit for providing common coefficient signals and for providing control signals to said program memory, said program memory responding to said control signals from said store unit to provide said common control signals;
• a plurality of combinations of arithmetic element units and extended work store units each extended work store unit having first and second sctions and sequentially reading from said first and second sections respectively in response to said first and second common extended work store address signals, each of said extended work store units coupled to said program memory for receiving selected ones of said common control signals, each arithmetic element unit including a work store unit, having first and second sections, a multiplier, parallel coupled first and second register and logic units and a limiter all respectively coupled in a pipe line configuration and all coupled to said program memory for receiving selected ones of said common control signals, said limiter coupled to said multiplier, to said work store unit and to said extended work store unit for selectively applying calculated data thereto, each work store unit sequentially reading from said first and second sections respectively in response to said first and second common work store address signals, said multiplier being selectively coupled to said work store unit and to said extended work store unit, said multiplier being coupled to said coefficient store unit for receiving said common coefficient signals;
• control delay means coupled between said program memory and said second register and logic units for causing each calculation in said second register and logic unit to be delayed one clock period from the calculation in said first register and logic unit and for delaying the coefficients used in each calculation of said second register and logic unit one clock period from the coefficients used in each calculation in said first register and logic unit;
• and
• an external interface unit coupled to said control element means, to said external device means, to said arithmetic element controller means and said plurality of extended work store units for transferring data to and from said external unit and selected ones of said extended work store units said external interface unit transferring data to and from said control element means, said external device means and said arithmetic element controller means.

An arithmetic unit responsive to clock means providing clock pulses at a clock pulse rate defining a plurality of sequential clock periods, responsive to a source of addresses and responsive to control means providing common control signals, comprising:

• a source of operands coupled to respond to said clock means and coupled to said source of addresses for providing first and second operands during two sequential clock periods;
• a source of coefficients coupled to respond to said clock means and coupled to said source of addresses for providing coefficient data during two sequential clock periods;
• multiplier means coupled to said source of operands, coupled to said source of coefficients and coupled to said clock means to sequentially provide multiplier values during each of said two sequential clock periods;
• first and second register and logic units coupled to said multiplier means and coupled to said clock means, each of said first and second register and logic units having available at least two clock periods to perform their computations, said first and second register and logic units coupled to said control means for receiving said common control signals;
• one clock period control delay means coupled between said control means and said second register and logic unit;
• and
• means coupled to said first and second register and logic units for receiving computational results therefrom at a rate equal to said clock pulse rate.

In a processor system, the combination comprising:

• a plurality of arithmetic element units each including a work store unit, a multiplier coupled to said work store unit and first and second register and arithmetic logic units coupled in parallel to aid multiplier, each of said work store units storing blocks of data words;
• a plurality of extended work storage units each for storing blocks of data words, one of said extended work store units associated with each arithmetic element unit;
• and
• an arithmetic element controller that includes an address generator coupled to each of said work store units and to each of said extended work store units, a program memory coupled to each of said multipliers and to each of said first and second register and arithmetic logic units and a coefficient store unit being coupled to each of said multiplier units and to each of said first and second register and arithmetic logic units, said program memory including a section storing a plurality of subroutines and a section storing an executive routine for addressing groups of said subroutines, said coefficient store unit including a section storing a subroutine address table for providing starting subroutine addresses to said section of said program memory storing an executive routine.

A processor system comprising:

• a plurality of calculating means;
• a plurality of work store memories, one for each calculating means;
• a plurality of extended work store memories, one for each calculating means;
• a control signal storage means commonly connected to each of said plurality of calculating means;
• a plurality of circuit means, each having two input circuits respectively coupled to receive outputs from the associated one of said plurality of work store memories and the associated one of said extended work store memories and each having an output circuit connected to the associated one of said plurality of calculating means for selectively coupling the output of said associated one of said plurality of work store memories and the output of said associated one of said plurality of extended work store memories to said calculating means;
• an extended work store access controller connected to each of said plurality of extended work store memories;
• an address generator providing enabling signals to said extended work store access controller and to each of said plurality of work store memories;
• and
• a program memory providing timing control signals connected to each of said plurality of circuit means, to said control signal storage means, to said address generator and to said extended work store access controller, for enabling an addressed extended work store memory to load data into said associated one of said plurality of calculating means, for providing priority control to said associated one of said plurality of work store memories and said associated one of said plurality of calculating means to perform arithmetic operations and storing of intermediate arithmetic results in said associated one of said plurality of work store memories and for operating said extended work store access controller to enable an addressed extended work store memory to receive arithmetic results from the associated one of said plurality of calculating means.