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US 4,541,045 AGranted
Microprocessor architecture employing efficient operand and instruction addressing
AssigneeRacal-Milgo, Inc.
InventorPhilip F. Kromer, III
Life of this patent
Estimating the term…
Abstract
A two-bus, two instruction type, pipelined microprocessor having a control means which orders application of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation.
Claims16
In a computer processor, the structure comprising:
- memory means for storing instructions and operands and addressable during each of a series of addressing intervals by one address comprising either an operand address or an instruction address and responsive to an operand address for outputting an operand and to an instruction address for outputting an instruction;
- a data bus for conducting the operands and instructions outputted by said memory means;
- address instruction decoder means for receiving an instruction from said data bus and for decoding said instruction and providing a data address request signal indicating whether the instruction does or does not require an operand fetch and for providing address control signals;
- address generation means for receiving said address control signals from said address instruction decoder means and responsive thereto for producing operand addresses for said memory means and for producing instruction addresses;
- means supplied with said operand and instruction addresses and responsive to a first control signal to apply a said instruction address to said memory means, responsive to a second control signal to apply a said operand address to said memory means, responsive to a third control signal to buffer a said operand address thereby producing a buffered operand address, and responsive to a fourth control signal to apply a said buffered operand address to said memory means;
- and
- logic means responsive to said data address request signal for generating said first, second, third and fourth control signals.
4 more elements
A microprocessor comprising:
- memory means for storing instructions and operands and addressable during successive units of time for outputting during each unit of time one data item comprising either a selected instruction or a selected operand;
- an address bus means for serially conducting addresses to said memory means;
- an output bus means for receiving instructions and operands outputted by said memory means and for conducting said instructions and said operands;
- operation means for receiving the instructions and operands conducted by said output bus means and for performing operations on said operands in accordance with said instructions;
- and
- control means for receiving said instructions from said output bus means and for decoding said instructions and responsive to said decoding for generating instruction addresses and data addresses and serially applying them to said address bus means in such an order that said memory means is addressed by either an instruction or operand address conducted by said address bus means during each said unit of time in which an address may be presented to said memory means.
3 more elements
A microprocessor comprising:
- an operation execution means responsive to supplied instructions for performing operations on supplied operands;
- a memory means having a single address bus and a single output bus and addressable during successive cycles by a serial sequence of addresses including instruction addresses and operand addresses applied on said address bus and responsive to said addresses to output a corresponding serial sequence of instructions and operands, a said instruction including information indicating an operation to be performed by said operation execution means, a said operand to be operated upon by said operation execution means, said operation execution means being connected to receive instructions and operands from said output bus;
- means for receiving instructions from said output bus for generating instruction and operand addresses, and for producing a signal indicating whether a received instruction does or does not require an operand from said memory means;
- and
- means responsive to said signal indicating whether a said instruction does or does not require an operand from said memory means for sequentially interleaving said instruction addresses and operand addresses on said address bus and for ordering presentation of instructions and operands outputted by said memory means to said operation execution means such that an instruction or operand address is presented each cycle to said memory means and a corresponding instruction or operand is outputted on said output bus each cycle and such that instructions and corresponding operands arrive in correct sequence for execution at said operation execution means.
2 more elements
In a microprocessor having a means for generating instruction and operand addresses for a memory, said memory being addressable by one of said addresses during each of a series of addressing intervals to output either an instruction or an operand, the apparatus comprising:
- buffer means for buffering an operand address generated by said generating means to produce a buffered operand address;
- means supplied with instructions outputted from said memory for generating a signal indicating an instruction outputted from said memory does or does not require an operand fetch;
- and
- control means responsive to said signal to generate control signals indicating whether in a particular addressing interval (1) a buffered operand address is to be applied to said memory, (2) an unbuffered operand address is to be applied to said memory, or (3) an instruction address is to be applied to said memory, and for applying an instruction address, an operand address or a buffered operand address to said memory in accordance with said control signals.
1 more element
Dependencies are inferred from the claim text.