Back to results
US 4,540,948 AGranted
8-Phase phase-shift keying demodulator
AssigneeNEC Corporation
InventorToshihiko Ryu
Life of this patent
Estimating the term…
Abstract
A demodulator features a circuit wherein a signal to effect carrier recovery and elimination of intersymbol interference etc. is produced by digitizing and processing demodulated signals in a manner that in the case of phase deviations due to noise or the like, the deviations fall within zones having predetermined digital identifications enabling the generation of appropriate digital correction signals via which the above mentioned signal production is controlled.
Claims12
An 8-phase phase-shift keying demodulator for demodulating an 8-phase phase-modulated signal applied thereto, said demodulator including:
- a voltage-controlled oscillator (6) controlled by an automatic phase control signal for carrier recovery;
- a first phase detector (2) supplied with said phase-modulated signal for coherent detection thereof using the output of said voltage-controlled oscillator;
- a second phase detector (3) supplied with said phase-modulated signal for coherent detection thereof using the .pi./2-radian phase-shifted output of said voltage-controlled oscillator;
- an adder (8) for adding the outputs of said first and second phase detector;
- a subtractor (9) for making subtraction of the outputs of said first and second phase detector;
- first through fourth binary decision circuits (10), (11), (12), and (13) coupled to said first phase detector, said adder, said subtractor, and said second phase detector, respectively, and generating binary signals D1, D2, D3, and D4, respectively;
- a code converter (14) for receiving said binary signals D1, D2, D3, and D4 and generating code-converted outputs,
- wherein the improvement comprises:
- a first means receiving the outputs of said first and second detector, generating error signals E.sub.PL and E.sub.PU which are components in the direction of the X coordinate axis on a phase plane and also generating error signals E.sub.QU and E.sub.QL which are components in the direction of the Y coordinate axis on said phase plane;
- a second means receiving the signals E.sub.PU, E.sub.PL, E.sub.QU, E.sub.QL, D2, and D4, and generating error signals Y.sub.P ' and Y.sub.Q ' according to the signals received;
- a third means receiving said error signals Y.sub.P ', Y.sub.Q ', D1 and D3 and generating error signals Y.sub.P and Y.sub.Q ;
- and
- a control signal generator which makes subtraction of said error signals Y.sub.P and Y.sub.Q for producing said automatic phase control signal;
- in which the signals Y.sub.P ', Y.sub.Q ', Y.sub.P, and Y.sub.Q satisfy the following logic equations,
- Y.sub.P '=E.sub.PU .multidot.(D2.sym.D4)+E.sub.PL .multidot.(D2.sym.D4)
- Y.sub.Q '=E.sub.QU .multidot.(D2.sym.D4)+E.sub.QL .multidot.(D2.sym.D4)
- Y.sub.P =Y.sub.P '.sym.D1.sym.D3
- Y.sub.Q =Y.sub.Q '.sym.D1.sym.D3.
15 more elements
Dependencies are inferred from the claim text.