Tri-state type driver circuit
AssigneeThe United States of America as represented by the Secretary of the Air Force
InventorsJohn J. Ennis, Robert K. Booher
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Abstract
An FET complementary pair provides the output to a data line. A data input line is coupled to the gate of the P-FET via an OR gate configuration, and to the gate of the N-FET via an AND gate configuration. The output of each gate configuration is cross-connected to an input of the other. When the input data state changes, the two gate configurations provide delays which are effectively in tandem, so that the FET which was ON is first turned OFF, and after a short delay the other is turned ON. This delay ensures that both FET's are not ON at the same time, which prevents an undesirable power flow. To provide a high impedance "float" state, an enable input and its complement are connected to the AND and OR gate configurations respectively.
Claims1
A tristate driver circuit having first and second logic states which are approximately the potentials at the positive and negative poles of a direct-current bias supply and a "float" state which is an intermediate potential at high impedance, said driver circuit comprising a P-type and an N-type field effect transistors, each having a source, a drain and a gate terminal, with the drain terminals of both transistors connected to a driver output line, the source terminals of the P-type and the N-type transistors connected respectively to the positive and negative poles of the direct-current bias supply;
- an OR gate means having three inputs, and having an output connected to the gate terminal of said P-type transistor, with the OR gate means comprising a NOR gate followed by an odd number of inverters;
- an AND gate means having three inputs and having an output connected to the gate terminal of said N-type transistor, with the AND gate means comprising a NAND gate followed by an odd number of inverters;
- wherein the NOR gate, the NAND gate, and each inverter comprises P-type and N-type field effect transistors, each transistor having source, gate, and drain electrodes, all of said transistors being part of a single integrated circuit chip;
- said OR gate means and AND gate means each having its output connected to an input of the other;
- an enable input coupled to an input of the AND gate means and inverted as an input of the OR gate means, so that in response to one signal condition at the enable input a first logic state is applied to the AND gate means, and thereby the outputs of the OR and AND gate means are at the first and second logic states respectively, to turn off both of said transistors regardless of the logic levels at the other inputs, to place said driver output line at the "float" state;
- a driver input line connected to inputs of both the OR gate means and the AND gate means for supplying logic signals at the first and second states alternately, so that with an enable signal condition at the input, which provides a second logic state input signal to the OR gate means and a first logic state input signal to the AND gate means, the driver circuit repeats the logic signal from the driver input line in inverted form to the driver output line, the first state at the output line having the P-type transistor on and the N-type transistor off, and vice versa for the second state at the output line, and AND gate means and OR gate means each providing some delay effectively in tandem, so that in resonse to a change of state at the driver input line the transistor which is on is first turned off, and after a short delay the transistor which was off is turned on, so that during a change between the first and second logic states at the output there is a definite interval during which the output is at the high-impedance "float" state.
Dependencies are inferred from the claim text.